Granted Patent B2

US 12,634,176 · App. 18/782,901 · Granted May 19, 2026

Inventors: Chulwoo Kim (Seoul, KR); Hyo Shin Kang (Seoul, KR); Yoon Jae Choi (Seoul, KR); Hwaseok Shin (Seoul, KR); Chang-Min Sim (Seoul, KR)

Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

H04L25/03057

Abstract

Claims (42)

1 . A decision feedback equalizer comprising:

a summator configured to receive a gray code-based 4-level pulse amplitude modulation (PAM-4) signal, a first bit signal, and a second bit signal, and to output an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first bit signal and the second bit signal; and

a decoder configured to receive the input voltage, a first reference voltage, a second reference voltage, a third reference voltage of the PAM-4 signal, and to output the first bit signal and the second bit signal,

wherein the decoder includes:

a first comparator configured to output the first bit signal by comparing a magnitude of the input voltage with a magnitude of the first reference voltage; and

a second comparator configured to output the second bit signal by comparing charge-discharge intensities of the input voltage and the second and third reference voltages.

2 . The decision feedback equalizer of claim 1 , wherein the second comparator is further configured to:

when the input voltage is greater than the second reference voltage and less than the third reference voltage, output the second bit signal as “0”; and

when the input voltage is less than the second reference voltage and greater than the third reference voltage, output the second bit signal as “1”.

3 . The decision feedback equalizer of claim 1 , wherein the summator includes:

a first tap configured to output an odd signal of the input voltage using odd bits of the first and second bit signals; and

a second tap configured to output an even signal of the input voltage using even bits of the first and second bit signals.

4 . The decision feedback equalizer of claim 1 , wherein the summator is further configured to:

when the first and second bit signals are “1” and “0”, respectively, add a first coefficient to the voltage level of the PAM-4 signal;

when the first and second bit signals are “1” and “1”, respectively, add a second coefficient to the voltage level of the PAM-4 signal;

when the first and second bit signals are “0” and “1”, respectively, add a third coefficient to the voltage level of the PAM-4 signal; and

when the first and second bit signals are “0” and “0”, respectively, add a fourth coefficient to the voltage level of the PAM-4 signal.

5 . The decision feedback equalizer of claim 1 , further comprising:

a continuous time linear equalizer configured to receive a data signal, to uniformly equalize all frequency components of the data signal, and to output the PAM-4 signal;

a variable gain amplifier configured to receive the PAM-4 signal and to amplify intervals between the voltage level of the PAM-4 signal and the first to third reference voltages; and

a compensation circuit configured to keep a common mode of the summator uniform.

6 . A method of operating a decision feedback equalizer comprising a summator and a decoder, the method comprising:

receiving, by the summator, a gray code-based 4-level pulse amplitude modulation (PAM-4) signal, a first bit signal, and a second bit signal, and outputting an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first bit signal and the second bit signal; and

receiving, by the decoder, the input voltage and first to third reference voltages of the PAM-4 signal, and outputting the first bit signal and the second bit signal,

wherein the outputting of the first bit signal and the second bit signal includes:

outputting the first bit signal by comparing a magnitude of the input voltage with a magnitude of the first reference voltage; and

outputting the second bit signal by comparing charge-discharge intensities of the input voltage and the second and third reference voltages.

7 . The method of claim 6 , wherein the outputting of the second bit signal further includes:

when the input voltage is greater than the second reference voltage and less than the third reference voltage, outputting the second bit signal as “0”; and

when the input voltage is less than the second reference voltage and greater than the third reference voltage, outputting the second bit signal as “1”.

8 . The method of claim 6 , wherein the outputting of the input voltage includes:

outputting an odd signal of the input voltage using odd bits of the first and second bit signals; and

outputting an even signal of the input voltage using even bits of the first and second bit signals.

9 . The method of claim 6 , wherein the outputting of the input voltage includes:

when the first and second bit signals are “1” and “0”, respectively, adding a first coefficient to the voltage level of the PAM-4 signal;

when the first and second bit signals are “1” and “1”, respectively, adding a second coefficient to the voltage level of the PAM-4 signal;

when the first and second bit signals are “0” and “1”, respectively, adding a third coefficient to the voltage level of the PAM-4 signal; and

when the first and second bit signals are “0” and “0”, respectively, adding a fourth coefficient to the voltage level of the PAM-4 signal.

10 . The method of claim 6 , further comprising:

receiving a data signal, uniformly equalizing all frequency components of the data signal, and outputting the PAM-4 signal;

receiving the PAM-4 signal and amplifying intervals between the voltage level of the PAM-4 signal and the first to third reference voltages; and

keeping a common mode of the outputting of the input voltage uniform.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (23)