Memory device and operation method thereof
Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory device can include a memory array and a peripheral circuit. The memory array can include a first and a second memory string. The peripheral circuit is configured to perform a first verification operation during a first loop of a program operation to program the first memory string. During a pre-pulse phase of the first verification operation, a pass voltage is applied to a first select line coupled to first select gate transistor of the second memory string for a first duration. The peripheral circuit is configured to perform a second verification operation during a second loop of the program operation that is after the first loop. During a pre-pulse phase of the second verification operation, a pass voltage is applied to the first select line for a second duration shorter than the first duration.
1 . A memory device, comprising:
a memory array comprising:
a first memory string comprising first memory cells; and
a second memory string comprising a first select gate transistor coupled to a first select line, a second select gate transistor, and second memory cells positioned between the first select gate transistor and the second select gate transistor;
a peripheral circuit coupled to the memory array and configured to perform a program operation to program the first memory string, wherein the program operation comprises:
performing, during a first loop of the program operation to program the first memory string, a first verification operation, wherein performing the first verification operation comprises:
during a first pre-pulse phase, applying, for a first duration, a first select voltage to the first select line; and
performing, during a second loop of the program operation, a second verification operation, wherein performing the second verification operation comprises:
during a second pre-pulse phase, applying, for a second duration, the first select voltage to the first select line,
wherein the second loop is after the first loop, and the second duration is shorter than the first duration.
2 . The memory device of claim 1 , wherein the first memory string is a selected memory string, the second memory string is an unselected memory string, the first select gate transistor is a drain select gate transistor, the second select gate transistor is a source select gate transistor, and the first select line is a drain select line.
3 . The memory device of claim 1 , wherein:
performing the first verification operation comprises:
during a first sense phase, verifying whether a first memory cell of the first memory cells is in a first programmed state,
performing the second verification operation comprises:
during a second sense phase, verifying whether a second memory cell of the first memory cells is in a second programmed state, and
the first programmed state is lower than the second programmed state.
4 . The memory device of claim 3 , wherein the program operation comprises:
performing, during a third loop of the program operation, a third verification operation, wherein performing the third verification operation comprises:
during a third pre-pulse phase, applying, for a third duration, the first select voltage to the first select line,
wherein the third loop is after the second loop, and the third duration is shorter than the second duration.
5 . The memory device of claim 4 , wherein performing the third verification operation comprises:
during a third sense phase, verifying whether a third memory cell of the first memory cells is in a third programmed state, wherein the third programmed state is higher than the second programmed state.
6 . The memory device of claim 5 , wherein the first memory cells are triple-level cells programmable to one of seven programmed states P1, P2, P3, P4, P5, P6 and P7 in an ascending order, and
wherein the first programmed state comprises at least one of P1, P2 or P3, the second programmed state comprises at least one of P4 or P5, and the third programmed state comprises at least one of P6 or P7.
7 . The memory device of claim 3 , wherein performing the first verification operation comprises:
in response to determining that the first programmed state is lower than a first threshold state, applying the first select voltage to the first select line for the first duration, and
wherein performing the second verification operation comprises:
in response to determining that the second programmed state is higher than or equal to the first threshold state and lower than a second threshold state, applying the first select voltage to the first select line for the second duration.
8 . The memory device of claim 3 , wherein performing the second verification operation comprises:
after applying a first verify voltage to a first word line coupled to the second memory cell of the first memory cells, applying a second verify voltage to the first word line, wherein the second verify voltage is higher than the first verify voltage.
9 . The memory device of claim 3 , wherein performing the first verification operation comprises:
during the first sense phase, applying a ground voltage to the first select line.
10 . The memory device of claim 3 , wherein the first memory string comprises a third select gate transistor, a fourth select gate transistor, wherein the first memory cells are positioned between the third select gate transistor and the fourth select gate transistor, and wherein the first verification operation comprises:
during the first pre-pulse phase and the first sense phase, applying the first select voltage to a second select line coupled to the third select gate transistor of the first memory string.
11 . The memory device of claim 10 , wherein the second select gate transistor of the second memory string and the fourth select gate transistor of the first memory string are coupled to a third select line,
wherein performing the first verification operation comprises:
during the first pre-pulse phase, applying a second select voltage to the third select line.
12 . The memory device of claim 3 , wherein performing the first verification operation comprises:
during the first pre-pulse phase and the first sense phase, applying a third verify voltage corresponding to the first programmed state to a second word line coupled to the first memory cell of the first memory cells.
13 . The memory device of claim 1 , wherein the program operation comprises:
performing, during a third loop of the program operation, a third verification operation without a pre-pulse phase before verifying whether a third memory cell of the first memory cells is in a third programmed state.
14 . A method of operating a memory device, comprising:
performing, during a first loop of a program operation to program a first memory string comprising first memory cells, a first verification operation, wherein performing the first verification operation comprises:
during a first pre-pulse phase, applying, for a first duration, a select voltage to a first select line coupled to a first select gate transistor of a second memory string, wherein the second memory string comprises the first select gate transistor, a second select gate transistor, and second memory cells positioned between the first select gate transistor and the second select gate transistor; and
performing, during a second loop of the program operation, a second verification operation, wherein performing the second verification operation comprises:
during a second pre-pulse phase, applying, for a second duration, the select voltage to the first select line,
wherein the second loop is after the first loop, and the second duration is shorter than the first duration.
15 . The method of claim 14 , wherein:
performing the first verification operation comprises:
during a first sense phase, applying a first verification voltage to a first word line coupled to a first memory cell of the first memory cells,
performing the second verification operation comprises:
during a second sense phase, applying a second verification voltage to a second word line coupled to a second memory cell of the first memory cells, and
the first verification voltage is lower than the second verification voltage.
16 . The method of claim 15 , wherein:
performing the first verification operation comprises:
in response to determining that a first programmed state corresponding to the first verification voltage is lower than a first threshold state, applying the select voltage to the first select line for the first duration, and
performing the second verification operation comprises:
in response to determining that a second programmed state corresponding to the second verification voltage is higher than or equal to the first threshold state and lower than a second threshold state, applying the select voltage to the first select line for the second duration.
17 . The method of claim 15 , comprising:
performing, during a third loop of the program operation, a third verification operation, wherein performing the third verification operation comprises:
during a third pre-pulse phase, applying, for a third duration, the select voltage to the first select line,
wherein the third loop is after the second loop, and the third duration is shorter than the second duration.
18 . The method of claim 17 , wherein performing the third verification operation comprises:
during a third sense phase, applying a third verification voltage to a third word line coupled to a third memory cell of the first memory cells, wherein the third verification voltage is higher than the second verification voltage.
19 . The method of claim 15 , comprising:
performing, during a third loop of the program operation, a third verification operation without a pre-pulse phase before a third sense phase.
20 . A memory system, comprising:
a memory device, comprising:
a memory array comprising:
a first memory string comprising first memory cells; and
a second memory string comprising a first select gate transistor coupled to a first select line, a second select gate transistor, and second memory cells positioned between the first select gate transistor and the second select gate transistor;
a peripheral circuit coupled to the memory array and configured to perform operations comprising:
performing, during a first loop of a program operation to program the first memory string, a first verification operation, wherein performing the first verification operation comprises:
during a first pre-pulse phase, applying, for a first duration, a select voltage to the first select line; and
performing, during a second loop of the program operation, a second verification operation, wherein the second verification operation comprises:
during a second pre-pulse phase, applying, fora second duration, the select voltage to the first select line, wherein the second loop is after the first loop, and the second duration is shorter than the first duration; and
a controller coupled to the memory device and configured to send signals to the memory device.