LOCKING CURRENT TRANSFORMER
A current transformer includes a first housing including a first handle portion and a first distal portion, a second housing including a second handle portion and a second distal portion, a first core mounted in in the first distal portion, a second core mounted in the second distal portion, and a lock attached to the second handle portion at a pivot point, wherein the first housing is rotationally coupled to the second housing about a fulcrum point and the lock is rotatable about the pivot point into a closed position wherein the lock engages the first handle portion and prevents the first handle portion and the second handle portion from rotating towards each other.
1 - 20 . (canceled)
21 . An assembly comprising:
a cord;
a plug operatively connected to the cord, wherein the plug is adapted to be plugged into a power monitor;
a first connection operatively connected to the cord, configured to be connected to a first current transformer; and
a memory chip situated within the plug.
22 . The assembly as recited in claim 21 , wherein the memory chip is adapted to store a first scale factor of the first current transformer.
23 . The assembly as recited in claim 21 , further comprising the first current transformer, wherein the first current transformer includes:
a first housing having a first handle portion and a first distal portion;
a second housing having a second handle portion, a second distal portion, and a connector connected to the first connection;
a first core, wherein the first core is mounted within the first distal portion; and
a second core, wherein the second core is mounted within the second distal portion.
24 . The assembly as recited in claim 22 , wherein the cable is a multi-wire cable including:
a first wire configured to connect between the first current transformer and the plug; and
a second wire configured to connect between the first current transformer and the plug.
25 . The assembly as recited in claim 24 , wherein the memory chip is connected to at least one of the first and second wires.
26 . The assembly as recited in claim 24 , further comprising:
a second connection connected to the cord, configured to be connected to a second current transformer.
27 . The assembly as recited in claim 26 , wherein the memory chip is adapted to store a second scale factor of the second current transformer.
28 . The assembly as recited in claim 26 , further comprising the second current transformer, wherein the second current transformer includes:
a third housing having a third handle portion and a third distal portion;
a fourth housing having a fourth handle portion, a fourth distal portion, and a connector connected to the second connection;
a third core, wherein the third core is mounted within the third distal portion; and
a fourth core, wherein the fourth core is mounted within the fourth distal portion.
29 . The assembly as recited in claim 28 , wherein the cable includes:
a third wire connecting between the second current transformer and the plug; and
a fourth wire connecting between the second current transformer and the plug.
30 . The assembly as recited in claim 29 , wherein the memory chip is connected to at least one of the first and second wires.
31 . The assembly as recited in claim 30 , wherein the memory chip is connected to at least one of the third and fourth wires.
32 . The assembly as recited in claim 30 , wherein the memory chip is connected to only one of the first, second, third, and fourth wires.
33 . The assembly as recited in claim 30 , wherein the memory chip is connected to its own two wires for connection to the power monitor separate from connection to the power monitor of the first, second, third, and fourth wires.
34 . A power monitor comprising:
a system on a chip (SoC);
a power and I/F circuit operatively connected to the SoC, wherein the power and I/F circuit is configured to connect to an interface to control a memory chip of a current transformer assembly; and
an analog-to-digital converter (A/D) operatively connected to the SoC, wherein the A/D includes:
a first connection configured to connect to a first wire of a first current transformer,
a second connection configured to connect to a second wire of the first current transformer;
a third connection configured to connect to a third wire of a second current transformer, and
a fourth connection configured to connect to a fourth wire of the second current transformer,
wherein the SoC, the power and I/F circuit, and A/D are configured to:
read a first scale factor for the first current transformer from the memory chip,
receive a first sensor value from the first current transformer,
compute a second sensor value from the first sensor value using the first scale factor, and
use the second sensor value to determine information about energy consumption in a building.
35 . The power monitor as recited in claim 34 , further comprising:
a first multiplexor connected in the second connection, wherein the first multiplexor is operatively connected to be enabled and disabled by the SoC, wherein in an enabled state, the first multiplexor is configured to connect the second wire to ground for reading from and writing to the memory chip, and in a disabled state, the first multiplexor is configured to connect the second wire to the A/D.
36 . The power monitor as recited in claim 35 , further comprising:
a second multiplexor connected in the fourth connection, wherein the second multiplexor is operatively connected to be enabled and disabled by the SoC, wherein in an enabled state, the second multiplexor is configured to connect the fourth wire to the power and I/F circuit for reading from and writing to the memory chip, and in a disabled state, the second multiplexor is configured to connect the fourth wire to the A/D.
37 . The power monitor as recited in claim 36 , wherein the first, second, third, and fourth connections are the only connections configured to connect to an interface of a current transformer assembly that includes the first and second current transformers.
38 . The power monitor as recited in claim 34 , further comprising:
a fifth connection configured to connect the power and I/F circuit to the memory chip; and
a multiplexor connected in the fourth connection, wherein the multiplexor is operatively connected to be enabled and disabled by the SoC, wherein in an enabled state, the multiplexor is configured to connect the fourth wire to ground for reading from and writing to the memory chip, and in a disabled state, the multiplexor is configured to connect the second wire to the A/D.
39 . The power monitor as recited in claim 34 , further comprising:
a fifth connection configured to connect the memory chip to ground.
40 . The power monitor as recited in claim 39 , further comprising:
a sixth connection configured to connect the power and I/F circuit to the memory chip.