Current and clock frequency management
Current sensing circuitry and clock management circuitry provide current and clock frequency management. In one example, an apparatus can include a voltage regulator, current sensing circuitry configured to: detect a current associated with the voltage regulator of a system-on-chip (SoC), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to: generate clocking signals for the SoC, select a gradient frequency alteration based on the detected current, and alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.
1 . An apparatus, comprising:
a voltage regulator;
current sensing circuitry configured to:
detect a current associated with the voltage regulator of a system-on-chip (SoC); and
determine when the current transitions from a first current to a second current, wherein the current transition indicates a mode transition of the SoC from an idle mode to an operation mode; and
clock management circuitry configured to:
generate clocking signals for the SoC;
select a gradient frequency alteration based on the detected current and the mode transition, wherein the gradient frequency alteration consists of a plurality of frequency alterations for the mode transition from the idle mode to the operation mode; and
alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.
2 . The apparatus of claim 1 , wherein the clock management circuitry is configured to alter the frequency of the clocking signals by decreasing the frequency of the clocking signals according to the gradient frequency alteration.
3 . The apparatus of claim 1 , wherein the clock management circuitry is further configured to alter the frequency of the clocking signals by increasing the frequency of the clocking signals according to the gradient frequency alteration.
4 . The apparatus of claim 1 , wherein the current transition from the first current to the second current includes a current transition of the SoC from a first state to a second state.
5 . The apparatus of claim 4 , wherein a plurality of gradient frequency alterations are selectable between the first state and the second state.
6 . The apparatus of claim 1 , wherein the gradient frequency includes a specific clock frequency to be utilized during a specific range of current values.
7 . The apparatus of claim 1 , wherein the clock management circuitry is further configured to apply a power mode transition termination during a power mode transition.
8 . The apparatus of claim 1 , wherein the current sensing circuitry is further configured to detect a transient current at the voltage regulator.
9 . The apparatus of claim 1 , wherein the voltage regulator includes a voltage sense feedback to compensate a current-resistance drop.
10 . A method, comprising:
detecting, by current sensing circuitry, a current associated with a voltage regulator of a system-on-chip (SoC);
determining, by the current sensing circuitry, when the detected current is transitioning from a first current to a second current, wherein the transitioning indicates a mode transition of the SoC from an idle mode to an operation mode;
generating, by clock management circuitry coupled to the current sensing circuitry, clocking signals for the SoC;
selecting, by the clock management circuitry, a gradient frequency alteration based on the detected current and the mode transition, wherein the gradient frequency alteration consists of a plurality of frequency alterations for the mode transition from the idle mode to the operation mode; and
altering, by the clock management circuitry, a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.
11 . The method of claim 10 , further comprising:
determining initiation of a low-power mode of the SoC;
detecting, by the current sensing circuitry, the current associated with the voltage regulator of the SoC is transitioning to a lower current in response to the initiation of the low-power mode; and
altering, by the clock management circuitry, the frequency to a corresponding lower frequency based on the gradient frequency alteration that corresponds to the lower current.
12 . The method of claim 11 , further comprising:
determining an early termination of the low-power mode of the SoC;
detecting, by the current sensing circuitry, the current associated with the SoC is transitioning to a higher current in response to the termination of the low-power mode; and
altering, by the clock management circuitry, the frequency to a corresponding higher frequency based on the gradient frequency alteration that corresponds to the higher current.
13 . The method of claim 10 , further comprising generating, by the clock management circuitry, the clock signals at the frequency identified by the gradient frequency alteration based on the detected current.
14 . The method of claim 13 , further comprising, generating, by the clock management circuitry, the clock signals in the absence of a predicted current or a predicted voltage associated with the SoC.
15 . A system, comprising:
a plurality of computing components coupled to a system-on-chip (SoC), wherein the SoC comprises:
a voltage regulator;
a current sensing circuit configured to:
detect a current associated with the voltage regulator of the SoC; and
determine when the current transitions from a first current to a second current, wherein the current transition indicates a mode transition of the SoC from an idle mode to an operation mode; and
clock management circuitry configured to:
generate clocking signals for the SoC;
select a gradient frequency alteration based on the current and the mode transition, wherein the gradient frequency alteration consists of a plurality of frequency alterations for the mode transition from the idle mode to the operation mode;
alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition; and
apply the clocking signals having the altered frequency to one or more of the plurality of computing components or to one or more components of the SoC.
16 . The system of claim 15 , wherein the voltage regulator is a Low Dropout Regulator (LDO).
17 . The system of claim 16 , wherein the current sensing circuit is a current mirror in the LDO.
18 . The system of claim 15 , wherein the plurality of frequency alterations are selected to minimize a current drop of the SoC during the mode transition.
19 . The system of claim 15 , wherein the current sensing circuit is a current transformer in a switching supply.
20 . The system of claim 15 , wherein the current sensing circuit is connected to the voltage regulator to determine an instantaneous or near-instantaneous current drawn by the SoC.