MULTI-TILE MEMORY MANAGEMENT
Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
1 . An apparatus comprising:
a first chiplet coupled with an interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource; and
a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache, wherein the memory controller is configured to enable access to a high-bandwidth memory (HBM) device.
2 . The graphics processor of claim 1 , further comprising cache circuitry coupled with the graphics processing resources via the interconnect, and wherein the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface, wherein the cache circuitry includes a level-2 (L2) cache, wherein the L2 cache includes a distributed cache having nodes interconnected via the interconnect network.
3 . (canceled)
4 . The graphics processor of claim 1 , wherein the memory side cache is configured to cache data associated with a memory access performed via the memory controller, wherein the memory-side cache includes a level-3 (L3) cache.
5 . The graphics processor of claim 1 , wherein one or more of the interposer, first chiplet, and second chiplet includes a 2.5-dimension (2.5D) arrangement, wherein the interposer includes an active interposer.
6 . (canceled)
7 . The graphics processor of claim 1 , wherein the graphics processing resource includes a plurality of functional units having a single instruction multiple thread (SIMT) architecture or a single instruction, multiple data (SIMD) architecture.
8 . The graphics processor of claim 7 , wherein the plurality of functional units includes one or more of a general-purpose graphics processor core, a tensor core, or a ray-tracing core.
9 - 10 . (canceled)
11 . A system comprising:
an interconnect to a system interface; and
a multi-die graphics processor coupled with the interconnect, the multi-die graphics processor comprising:
an interposer;
a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource;
a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache, wherein the memory controller is configured to enable access to a high-bandwidth memory (HBM) device.
12 . The system of claim 11 , further comprising cache circuitry coupled with the graphics processing resources via the interconnect, and wherein the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface, wherein the cache circuitry includes a level-2 (L2) cache, wherein the L2 cache includes a distributed cache having nodes interconnected via the interconnect network.
13 . (canceled)
14 . The system of claim 11 , wherein the memory side cache is configured to cache data associated with a memory access performed via the memory controller, wherein the memory-side cache includes a level-3 (L3) cache.
15 . The system of claim 11 , wherein one or more of the interposer, first chiplet, and second chiplet include a 2.5-dimension (2.5D) arrangement, wherein the interposer includes an active interposer.
16 . (canceled)
17 . The system of claim 11 , wherein the graphics processing resource includes a plurality of functional units having a single instruction multiple thread (SIMT) architecture or a single instruction, multiple data (SIMD) architecture.
18 . The system of claim 17 , wherein the plurality of functional units includes, or a ray-tracing core a general-purpose system core, a tensor core, or a ray-tracing core.
19 - 20 . (canceled)