Parity data in dynamic random access memory (DRAM)
Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.
1 . A method, comprising:
receiving user data from a non-volatile memory device at a controller of a dual in-line memory module (DIMM);
receiving parity data corresponding to the user data from a dynamic random access memory (DRAM) device at the controller; and
reconstructing the user data at the controller using the parity data.
2 . The method of claim 1 , further comprising regenerating the parity data in response to powering off and powering on the DRAM device.
3 . The method of claim 1 , further comprising receiving the parity data in response to a read failure.
4 . The method of claim 3 , further comprising reconstructing the user data in response to the read failure.
5 . The method of claim 4 , wherein the read failure is due to corrupted memory in the non-volatile memory device.
6 . The method of claim 1 , further comprising reading the user data and reconstructing the user data in one clock cycle.
7 . The method of claim 1 , further comprising generating the parity data at the controller by performing an error correction code (ECC) operation on the user data.
8 . The method of claim 1 , further comprising performing a RAID operation on the user data to generate the parity data at the controller.
9 . A dual in-line memory module (DIMM), comprising:
a dynamic random access memory (DRAM) device;
a non-volatile memory device coupled to the DRAM device, wherein the non-volatile memory device is configured to store user data; and
a controller coupled to the DRAM device and the non-volatile memory device, wherein the controller is configured to:
receive the user data from the non-volatile memory device; and
perform an error correction code (ECC) operation on the user data to regenerate parity data.
10 . The DIMM of claim 9 , wherein the controller is configured to perform the ECC operation on the user data to regenerate the parity data in response to powering on the DRAM device.
11 . The DIMM of claim 9 , wherein the controller comprises an error correction code (ECC) module configured to perform the ECC operation.
12 . The DIMM of claim 9 , wherein the ECC operation is an XOR operation.
13 . The DIMM of claim 9 , wherein the controller is configured to perform the ECC operation in one clock cycle.
14 . The DIMM of claim 9 , wherein the controller is configured to rewrite the parity data to the DRAM device in response to powering on the DRAM device.
15 . A dual in-line memory module (DIMM), comprising:
a controller configured to generate parity data based on user data;
a dynamic random access memory (DRAM) device configured to store the parity data; and
a non-volatile memory device configured to store the parity data prior to powering off the DRAM device; and
wherein the controller is configured to rewrite the parity data to the DRAM device in response to powering on the DRAM device.
16 . The DIMM of claim 15 , wherein the non-volatile memory device is configured to store the user data.
17 . The DIMM of claim 15 , wherein the non-volatile memory device is a 3D Cross-point device.
18 . The DIMM of claim 15 , wherein the controller is configured to generate the parity data based on the user data in response to receiving a write command.
19 . The DIMM of claim 18 , wherein the write command includes the user data.
20 . The DIMM of claim 15 , wherein the user data is queued for writing to the non-volatile memory device.