IP Library › Granted Patent US 12,586,056
Granted Patent B2
US 12,586,056 · App. 18/809,266 · Granted Mar 24, 2026

Microprocessor as a security layer

Inventor: Stefano Bianconi (Berlin, DE)
Assignee: SUMUP PAYMENTS LTD.
G06Q20/34G06K7/006G06K7/0091G06K7/10297G06Q20/20G07F7/0886G09G3/36H04B5/26G09G2310/02G09G2340/0435H04B5/70
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Quick Facts
Patent No.
US 12,586,056
App. No.
18/809,266
Granted
Mar 24, 2026
Kind
B2
Abstract

Various aspects of the disclosure generally relate to security for a credit card processing reader. Part of security for a reader is protecting sensitive components, for example components that access information from a credit card during a transaction. An alternative security configuration may include integrated circuits replacing portions of electrically active mesh. This may reduce the size and cost of a reader while maintaining its security with respect to published guidelines.

Claims (40)

1 . A credit card processing reader comprising:

a case;

a printed circuit board (PCB) coupled to the case, the PCB with a first side and a second side, the first and second sides parallel and opposite to one another;

an integrated circuit coupled to the first side of the PCB, the integrated circuit having a footprint defined by a boundary line drawn around the perimeter of the integrated circuit, the boundary line perpendicular to the plane of the integrated circuit and through the PCB, the integrated circuit having at an input/output (I/O) pin within the integrated circuit footprint and between the top of the integrated circuit and the first side of the PCB;

a first security mesh coupled to the PCB and including a plurality of electrical traces as part of an electrical circuit, the first security mesh existing on a plane parallel to the first and second sides, the first security mesh outside the footprint of the integrated circuit;

a via that extends through the PCB from the first side to the second side, the via entirely within the footprint of the integrated circuit; and

an electrode coupled to the second side of the PCB, the electrode configured to access data from a credit card during a credit card transaction, the electrode coupled to the via.

2 . The credit card processing reader of claim 1 wherein the first security mesh is entirely outside the footprint of the integrated circuit.

3 . The credit card processing reader of claim 1 further comprising:

a cover coupled to the second side of the PCB; and

a second security mesh coupled to the cover and including a plurality of electrical traces as part of an electrical circuit.

4 . The credit card processing reader of claim 1 wherein the first security mesh overlaps at least a portion of the integrated circuit footprint.

5 . The credit card processing reader of claim 4 wherein the second security mesh forms a plane parallel to the cover and has a surface area approximately equal to the surface area of the first security mesh added to the surface area of the integrated circuit.

6 . The credit card processing reader of claim 1 wherein the electrode is within the integrated circuit footprint.

7 . The credit card processing reader of claim 1 wherein the via traverses in a straight line from the first side of the PCB to the second side of the PCB.

8 . The credit card processing reader of claim 7 wherein the electrode is a secure card pin.

9 . The credit card processing reader of claim 1 wherein the via traverses through the PCB from the first side to the second side in a line having a plurality of turns, such that at least part of the via is not perpendicular to the PCB.

10 . The credit card processing reader of claim 1 wherein the electrode is one of a plurality of electrodes including a secure card pin, the I/O pin is one of a plurality of I/O pins, the via is one of a plurality of vias, the plurality of electrodes electrically coupled to the plurality of I/O pins through the plurality of vias and entirely within the integrated circuit footprint.

11 . The credit card processing reader of claim 10 where at least one of the plurality of vias extends outside the integrated circuit footprint.

12 . The credit card processing reader of claim 1 wherein the plurality of electrical traces of the first security mesh have a spacing between two immediately adjacent traces of no more than 150 micrometers.

13 . A credit card processing reader comprising:

a case;

a printed circuit board (PCB) coupled to the case, the PCB with a first side and a second side, the first and second sides parallel and opposite to one another;

a cover coupled to the second side of the PCB;

a security measure comprising:

a security mesh with a plurality of electrical traces, the security mesh coupled to the PCB and to the cover; and

a secure processor coupled to the first side of the PCB, the secure processor over, along a perspective axis that is perpendicular to the PCB, a portion of the PCB that is nonoverlapping on the PCB with the security mesh coupled to the PCB.

14 . The credit card processing reader of claim 13 wherein the plurality of electrical traces have a spacing between two immediately adjacent traces of no more than 150 micrometers.

15 . The credit card processing reader of claim 14 wherein the secure processor over a portion of the PCB is entirely nonoverlapping on the PCB with the security mesh coupled to the PCB.

16 . The credit card processing reader of claim 14 further comprising:

an input/output (I/O) pin coupled to the secure processor and between the top of the secure processor and the first side of the PCB;

a via extending through the PCB from the first side to the second side of the PCB; and

an electrode coupled to the second side of the PCB and electrically coupled to the via, the electrode configured to convey data from a credit card during a transaction.

17 . The credit card processing reader of claim 16 wherein the via traverses through the PCB from the first side to the second side in a line having a plurality of turns, such that the via is not entirely perpendicular to the PCB.

18 . The credit card processing reader of claim 16 wherein the via extends through the PCB in a straight line, the via electrically connected to the I/O pin, the electrode further comprising a secure card (SC) pin, the SC pin coupled to the secure processor through the via.

19 . The credit card processing reader of claim 13 further comprising:

an input/output (I/O) pin coupled to the secure processor and between the top of the secure processor and the first side of the PCB;

a via extending through the PCB from the first side to the second side of the PCB; and

an electrode coupled to the second side of the PCB and electrically coupled to the via, the electrode configured to convey data from a credit card during a transaction.

20 . The credit card processing reader of claim 19 wherein the via extends through the PCB in a straight line, the via electrically connected to the I/O pin, the electrode further comprising a secure card (SC) pin, the SC pin coupled to the secure processor through the via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2024
From: BIANCONI, STEFANO
To: SUMUP PAYMENTS LTD.
Reel/Frame 068388/0213 →
Continuity (3)
Continuation 18000235
Provisional Application 63082749 · Sep 24, 2020
Related Publication 20240412195A1 · Dec 12, 2024
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