Phase-locked loop circuit including a plurality of capacitor cells and method of controlling the same
A phase-locked loop circuit includes an oscillator including a plurality of capacitor cells, and a control logic circuit that receives an output from the oscillator. The control logic circuit compares a target frequency with a first frequency of a first signal output from the oscillator, generates a first input code to control at least a portion of the plurality of capacitor cells to output a signal having the target frequency based on the comparison, generates a first output code corresponding to the first input code when the first input code is within a predetermined range of input codes, and controls at least two capacitor cells from among the plurality of capacitor cells based on the first output code. The oscillator may output a second signal having a second frequency through an electrical path including capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells.
1 . A phase-locked loop circuit comprising:
an oscillator comprising a capacitor cell array including a plurality of capacitor cells, wherein each of the plurality of capacitor cells corresponds to a distinct row-column position in the capacitor cell array; and
a control logic circuit configured to receive an output from the oscillator,
wherein the control logic circuit is configured to
compare a target frequency with a first frequency of a first signal output from the oscillator,
generate a first input code based on the comparison of the target frequency with the first frequency,
generate a first output code based on the first input code when the first input code is within a predetermined range of input codes, and
adjust a state of at least two capacitor cells from among the plurality of capacitor cells based on the first output code, and
wherein the oscillator is configured to output a second signal having a second frequency through an electrical path comprising capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells.
2 . The phase-locked loop circuit of claim 1 , wherein the control logic circuit comprises:
a dithering circuit configured to dither the first input code and generate a dithering signal based on the dithered first input code; and
a decoder configured to decode the dithering signal and generate the first output code corresponding to the first input code based on the decoded dithering signal.
3 . The phase-locked loop circuit of claim 2 , wherein the control logic circuit is configured to
generate a locked control signal and a third input code based on a difference between the second frequency and the target frequency being less than a predetermined difference;
output a third output code corresponding to the third input code in response to the locked control signal; and
control a single capacitor cell from among the plurality of capacitor cells based on the third output code.
4 . The phase-locked loop circuit of claim 1 , wherein the control logic circuit is configured to
generate a second input code based on a difference between the second frequency and the target frequency being greater than or equal to a predetermined difference;
generate a second output code based on the second input code when the second input code is within the predetermined range of input codes; and
adjust a state of at least another two capacitor cells from among the plurality of capacitor cells based on the second output code.
5 . The phase-locked loop circuit of claim 1 , wherein the control logic circuit is configured to output a predetermined code as a second output code based on a second input code being outside the predetermined range of input codes.
6 . The phase-locked loop circuit of claim 5 , wherein the control logic circuit is configured to:
output an output code corresponding to a first boundary code of the predetermined range of input codes as the second output code based on the second input code being less than the first boundary code; or
output an output code corresponding to a second boundary code of the predetermined range of input codes as the second output code based on the second input code being greater than the second boundary code.
7 . The phase-locked loop circuit of claim 1 , further comprising:
a controller configured to generate control signals and control the control logic circuit based on the control signals,
wherein the controller is configured to:
generate a first control signal configured to cause the control logic circuit to generate an output code that adjusts a state of two or more capacitor cells from among the plurality of capacitor cells based on the target frequency being less than a reference frequency; and
generate a second control signal configured to cause the control logic circuit to generate an output code that adjusts a state of a single capacitor cell from among the plurality of capacitor cells based on the target frequency being greater than or equal to the reference frequency.
8 . The phase-locked loop circuit of claim 1 , further comprising:
a plurality of row control lines and a plurality of column control lines, respectively connected to the plurality of capacitor cells;
a row decoder connected to the plurality of row control lines; and
a column decoder connected to the plurality of column control lines,
wherein the row decoder is configured to decode the first output code to provide a first decoded output code, and select at least a portion of the plurality of row control lines based on the first decoded output code, and
the column decoder is configured to decode the first output code to provide a second decoded output code, and select at least a portion of the plurality of column control lines based on the second decoded output code.
9 . The phase-locked loop circuit of claim 1 , wherein the control logic circuit is configured to ground the at least two capacitor cells based on the first output code.
10 . The phase-locked loop circuit of claim 1 , wherein the control logic circuit is configured to connect the at least two capacitor cells to a power supply voltage based on the first output code.
11 . A method of controlling a phase-locked loop circuit, the method comprising:
comparing a target frequency with a first frequency of a first signal output from an oscillator of the phase-locked loop circuit;
generating a first input code based on the comparing;
generating a first output code based on the first input code when the first input code is within a predetermined range of input codes;
adjusting a state of at least two capacitor cells from among a plurality of capacitor cells based on the first output code, wherein each of the plurality of capacitor cells corresponds to a distinct row-column position in a capacitor cell array of the phase-locked loop circuit; and
outputting, by the oscillator, a second signal having a second frequency through an electrical path comprising capacitor cells from among the plurality of capacitor cells that are connected to a power supply voltage.
12 . The method of claim 11 , further comprising:
generating a second input code based on a difference between the second frequency and the target frequency being greater than or equal to a predetermined difference;
outputting a second output code based on the second input code when the second input code is within the predetermined range; and
adjusting a state of at least another two capacitor cells from among the plurality of capacitor cells based on the second output code.
13 . The method of claim 11 , further comprising:
generating a locked control signal and a third input code based on a difference between the second frequency and the target frequency being less than a predetermined difference;
generating a third output code corresponding to the third input code in response to the locked control signal; and
adjusting a state of a single capacitor cell from among the plurality of capacitor cells based on the third output code.
14 . The method of claim 11 , comprising at least one of:
outputting a second output code corresponding to a first boundary code of the predetermined range of input codes based on a second input code being less than the first boundary code; or
outputting a third output code corresponding to a second boundary code of the predetermined range of input codes based on a third input code being greater than the second boundary code.
15 . The method of claim 11 , wherein adjusting the state of the at least two capacitor cells comprises grounding the at least two capacitor cells, wherein the at least two capacitor cells are selected by the first output code.
16 . A phase-locked loop device comprising:
an oscillator comprising a plurality of capacitor cells respectively connected to a plurality of row control lines and a plurality of column control lines; and
a control logic circuit configured to receive an output from the oscillator,
wherein the control logic circuit is configured to output a first output code based on a result of comparison between a target frequency and a first frequency of a first signal output from the oscillator, wherein the first output code adjusts a state of at least two capacitor cells from among the plurality of capacitor cells, and
wherein the oscillator is configured to output a second signal having a second frequency through an electrical path comprising capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells, based on the first output code.
17 . The phase-locked loop device of claim 16 , wherein the control logic circuit is configured to:
generate a first input code based on the result of the comparison between the target frequency and the first frequency;
generate the first output code corresponding to the first input code based on a correspondence between an ordered plurality of input codes and a corresponding plurality of output codes; and
adjust the state of the at least two capacitor cells from among the plurality of capacitor cells based on the first output code,
wherein the adjusted state of the at least two capacitor cells is modified compared to a state of the at least two capacitor cells corresponding to a second output code, wherein the second output code corresponds to a second input code that is adjacent to the first input code in the ordered plurality of input codes.
18 . The phase-locked loop device of claim 17 , wherein the control logic circuit is configured to:
output an output code corresponding to a first boundary code of a predetermined range of input codes based on a third input code being less than the first boundary code; and
output an output code corresponding to a second boundary code of the predetermined range of input codes based on a fourth input code being greater than the second boundary code.
19 . The phase-locked loop device of claim 16 , wherein the control logic circuit is configured to ground the at least two capacitor cells based on the first output code.
20 . The phase-locked loop device of claim 19 , wherein the control logic circuit is configured to connect capacitor cells from among the plurality of capacitor cells other than the at least two capacitor cells to a power supply voltage.