HANDLING PIPELINE SUBMISSIONS ACROSS MANY COMPUTE UNITS
One embodiment provides an apparatus comprising an interconnect fabric comprising a processing cluster including an array of multiprocessors coupled to an interconnect fabric, scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors, each thread group comprising a plurality of threads. A first multiprocessor of the array of multiprocessors can be assigned to process a first thread group comprising a first plurality of threads including a first thread sub-group and a second thread sub-group. The second thread sub-group has a data dependency on the first thread sub-group and the first multiprocessor includes circuitry to cause threads of the second thread sub-group to sleep until the threads of the first thread sub-group have satisfied the data dependency.
1 - 20 . (canceled)
21 . An accelerator device comprising:
a processing cluster including an array of multiprocessors coupled to an interconnect fabric;
scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors; and
a multiprocessor of the array of multiprocessors to be assigned to process a first thread group comprising a plurality of threads, the multiprocessor including circuitry configured to:
execute a first thread sub-group and a second thread sub-group, the first thread sub-group and the second thread sub-group formed based on the first thread group and respectively include a plurality of threads, the second thread sub-group has a data dependency on the first thread sub-group; and
cause threads of the second thread sub-group to sleep until threads of the first thread sub-group have satisfied the data dependency.
22 . The accelerator device of claim 21 , wherein the multiprocessor includes circuitry to track an execution status of the first thread sub-group and is configured to execute instructions of the second thread sub-group based on a change in the execution status of the first thread sub-group.
23 . The accelerator device of claim 22 , wherein the change in the execution status of the first thread sub-group indicates that the first thread sub-group has satisfied the data dependency.
24 . The accelerator device of claim 23 , wherein the multiprocessor is configured to execute instructions of first thread sub-group to generate a first portion of an output data set and execute instructions of the second thread sub-group to generate a second portion of the output data set.
25 . The accelerator device of claim 21 , wherein the array of multiprocessors is configured to exchange data via the interconnect fabric.
26 . The accelerator device of claim 25 , wherein the interconnect fabric includes a fabric switch including a data crossbar.
27 . The accelerator device of claim 25 , comprising a plurality of memory interfaces coupled to the interconnect fabric to provide access to a plurality of memory devices.
28 . The accelerator device of claim 25 , comprising an input/output (I/O) interface coupled to the interconnect fabric to provide access to I/O devices.
29 . A method comprising:
distributing a plurality of thread groups across an array of multiprocessors, the array of multiprocessors coupled to an interconnect fabric comprising one or more fabric switches to couple the array of multiprocessors to a plurality of memory devices;
assigning a multiprocessor of the array of multiprocessors to process a first thread group comprising a first plurality of threads;
executing instructions of a first thread sub-group and instructions of a second thread sub-group via circuitry of the multiprocessor, the first thread sub-group and the second thread sub-group formed based on the first thread group and respectively include a plurality of threads, the second thread sub-group having a data dependency on the first thread sub-group; and
causing threads of the second thread sub-group to sleep until threads of the first thread sub-group have satisfied the data dependency via circuitry of the multiprocessor.
30 . The method of claim 29 , wherein the multiprocessor includes circuitry to track an execution status of the first thread sub-group.
31 . The method of claim 30 , comprising executing instructions of the second thread sub-group based on a change in the execution status of the first thread sub-group.
32 . The method of claim 31 , wherein the change in the execution status of the first thread sub-group indicates that the first thread sub-group has satisfied the data dependency.
33 . The method of claim 32 , comprising executing instructions of first thread sub-group to generate a first portion of an output data set and executing instructions of the second thread sub-group to generate a second portion of the output data set.
34 . The method of claim 29 , comprising:
providing the array of multiprocessors access to a plurality of memory devices via a plurality of memory interfaces coupled to the interconnect fabric;
providing the array of multiprocessors access to input/output (I/O) devices via an I/O interface coupled with the interconnect fabric; and
exchanging data between the array of multiprocessors via the interconnect fabric.
35 . A data processing system comprising:
a memory device; and
an accelerator device comprising a processing cluster including an array of multiprocessors coupled to an interconnect fabric, scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessor, and a multiprocessor of the array of multiprocessors to be assigned to process a first thread group comprising a first plurality of threads, the multiprocessor comprising circuitry configured to:
execute a first thread sub-group and a second thread sub-group, the first thread sub-group and the second thread sub-group formed based on the first thread group and respectively include a plurality of threads, the second thread sub-group having a data dependency on the first thread sub-group; and
cause threads of the second thread sub-group to sleep until threads of the first thread sub-group have satisfied the data dependency.
36 . The data processing system of claim 35 , wherein the multiprocessor includes circuitry to track an execution status of the first thread sub-group and execute instructions of the second thread sub-group based on a change in the execution status of the first thread sub-group.
37 . The data processing system of claim 36 , wherein the change in the execution status of the first thread sub-group indicates that the first thread sub-group has satisfied the data dependency.
38 . The data processing system of claim 37 , wherein the multiprocessor is configured to execute instructions of first thread sub-group to generate a first portion of an output data set and execute instructions of the second thread sub-group to generate a second portion of the output data set.
39 . The data processing system of claim 35 , wherein the array of multiprocessors is configured to exchange data via the interconnect fabric.
40 . The data processing system of claim 39 , comprising a plurality of memory interfaces coupled to the interconnect fabric to provide access to a plurality of memory devices and an input/output (I/O) interface coupled to the interconnect fabric to provide access to I/O devices.