Memory device, operation method thereof, memory system, and memory controller
According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array including a plurality of memory cells. A preset number of the memory cells may form a code word. The memory device may include a peripheral circuit coupled with the memory cell array. The peripheral circuit may be configured to obtain M first results corresponding to at least one code word at M target read voltages. The peripheral circuit may be configured to obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model. The peripheral circuit may be configured to determine a target valley voltage based on the predicted valley voltage. The target valley voltage may be configured as a read voltage for a read operation on the at least one code word.
1 . A memory device, comprising:
a memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a code word; and
a peripheral circuit coupled with the memory cell array and configured to:
obtain M first results corresponding to at least one code word at M target read voltages, wherein the first result comprises a number of bits which represents the number of flipped bits in the at least one code word in two read results at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model, wherein the preset function model represents a relationship between the first results and the target read voltages, and wherein M is an integer greater than or equal to 1; and
determine a target valley voltage based on the predicted valley voltage, wherein the target valley voltage is configured as a read voltage for a read operation on the at least one code word.
2 . The memory device of claim 1 , wherein the preset function model comprises a quadratic function model comprising the following function relation:
y
=
a
(
x
+
b
)
2
+
c
wherein y is the first result, x is the target read voltage, b is to represent a prediction parameter, a is a first parameter, and c is a second parameter.
3 . The memory device of claim 2 , wherein the peripheral circuit is configured to:
obtain N sets of prediction parameters according to the M first results, the M target read voltages and the quadratic function model, wherein
N
=
C
M
i
,
i is an integer, and 1≤i≤M; and
obtain the predicted valley voltage according to the N sets of prediction parameters.
4 . The memory device of claim 3 , wherein i is equal to 1, wherein both of the first parameter and the second parameter are constants, and wherein the peripheral circuit is configured to:
obtain the N sets of prediction parameters according to the M first results, the M target read voltages, the quadratic function model, the first parameter and the second parameter.
5 . The memory device of claim 3 , wherein i is equal to 2, wherein the first parameter is a variable and the second parameter is a constant, and wherein the peripheral circuit is configured to:
obtain the N sets of prediction parameters and the first parameter according to the M first results, the M target read voltages, the quadratic function model and the second parameter.
6 . The memory device of claim 3 , wherein i is equal to 3, wherein both of the first parameter and the second parameter are variables, and wherein the peripheral circuit is configured to:
obtain the N sets of prediction parameters, the first parameter and the second parameter according to the M first results, the M target read voltages and the quadratic function model.
7 . The memory device of claim 4 , wherein i is equal to M, and wherein the peripheral circuit is configured to:
obtain one set of prediction parameters according to the M first results, the M target read voltages and the quadratic function model; and
take the prediction parameters as the predicted valley voltage.
8 . The memory device of claim 4 , wherein i is less than M, and wherein the peripheral circuit is configured to:
determine outliers of the N sets of prediction parameters; and
take a median or an average value of the remaining prediction parameters after removal of the outliers from the N sets of prediction parameters as the predicted valley voltage.
9 . The memory device of claim 3 , wherein the memory cell array comprises memory cells each having a plurality of storage bits, wherein the plurality of storage bits correspond to a plurality of pages respectively, wherein at least one of the pages corresponds to a plurality of stages, wherein the plurality of stages comprise a first stage and a second stage, wherein a read voltages of the second stage is less than a read voltage of the first stage, and wherein the peripheral circuit is configured to:
obtain at least one of a predicted valley voltage of the second stage or predicted valley voltages of the remaining first stages having lower read voltages in the plurality of stages according to the predicted valley voltage of the first stage of each of the plurality of pages; and
perform a read operation on the at least one code word according to the predicted valley voltage of the first stage and the predicted valley voltage of the second stage of each page.
10 . The memory device of claim 9 , wherein the peripheral circuit is configured to:
determine the predicted valley voltage of each stage as the target valley voltage according to successful error correction decoding on a read result of the read operation;
re-obtain a first result corresponding to the at least one code word at one target read voltage of the first stage according to failed error correction decoding on the read result of the read operation;
re-obtain the prediction parameters according to a plurality of first results obtained and a plurality of target read voltages in conjunction with the preset function model; and
perform the read operation on the at least one code word based on the re-obtained prediction parameters until the error correction decoding on the read result of the read operation is successful.
11 . The memory device of claim 1 , wherein the peripheral circuit is configured to:
obtain a preset threshold according to a corresponding first result at a first target read voltage of the M target read voltages, wherein the preset threshold is configured to represent a first result corresponding to a maximum value in an effective range of predicted valley voltage; and
take the predicted valley voltage as the target valley voltage according to the first result corresponding to the predicted valley voltage being less than the preset threshold.
12 . The memory device of claim 1 , wherein the memory cell array comprises memory cells each having a plurality of storage bits, wherein the plurality of storage bits correspond to a plurality of pages respectively, wherein at least one of the pages corresponds to a plurality of stages, and wherein the peripheral circuit is configured to:
after determining a target valley voltage of the at least one code word at a target stage, respectively determine target valley voltages of other stages in the plurality of stages than the target stage.
13 . The memory device of claim 1 , wherein the peripheral circuit is configured to:
read a storage data of the at least one code word at the first read voltage to obtain a second result;
read the storage data of the at least one code word at the second read voltage to obtain a third result;
perform a logic operation on the second result and the third result to obtain a fourth result; and
count the number of bits in the fourth result that represent flip of bits in the third result compared to the second result to obtain the first result.
14 . The memory device of claim 13 , wherein the peripheral circuit comprises:
a first latch configured to store the second result;
a second latch configured to store the third result; and
a third latch configured to store the fourth result.
15 . A memory system, comprising:
one or more memory devices, each of the one or more memory device comprising:
a memory cell array comprising a plurality of memory cells, wherein a preset number of the memory cells form a code word; and
a peripheral circuit coupled with the memory cell array and configured to:
obtain M first results corresponding to at least one code word at M target read voltages, wherein the first result comprises a number of bits which represents the number of flipped bits in the at least one code word in two read results at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model, wherein the preset function model represents a relationship between the first results and the target read voltages, and wherein M is an integer greater than or equal to 1; and
determine a target valley voltage based on the predicted valley voltage, wherein the target valley voltage is configured as a read voltage for a read operation on the at least one code word; and
a memory controller coupled with the one or more memory devices and configured to control the one or more memory devices.
16 . The memory system of claim 15 , wherein:
the memory controller is configured to send a data acquisition instruction,
the data acquisition instruction indicates acquisition of the target valley voltage,
the memory device is configured to receive the data acquisition instruction, obtain the target valley voltage, and send information comprising the target valley voltage to the memory controller, and
the memory controller is further configured to perform the read operation on data stored in the memory device according to the target valley voltage in the information.
17 . The memory system of claim 16 , wherein the memory controller is further configured to perform an error correction decoding operation on a read result of the read operation.
18 . A memory controller, comprising:
a control component configured to:
obtain M first results corresponding to at least one code word at M target read voltages, wherein the first result comprises a number of bits which represents the number of flipped bits in the at least one code word in two read results at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model, wherein the preset function model represents a relationship between the first results and the target read voltages, and wherein M is an integer greater than or equal to 1; and
determine a target valley voltage based on the predicted valley voltage, wherein the target valley voltage is configured as a read voltage for a read operation on the at least one code word,
wherein the memory controller is coupled with at least one memory device, wherein the memory device comprises a plurality of memory cells, and wherein a preset number of the memory cells forming a code word.
19 . The memory controller of claim 18 , wherein the preset function model comprises a quadratic function model comprising the following function relation:
y
=
a
(
x
+
b
)
2
+
c
wherein y is the first result, x is the target read voltage, b is to represent a prediction parameter, a is a first parameter, and c is a second parameter.
20 . The memory controller of claim 19 , wherein the control component is configured to:
obtain N sets of prediction parameters according to the M first results, the M target read voltages and the preset function model, wherein
N
=
C
M
i
,
i is an integer, and 1≤i≤M; and
obtain the predicted valley voltage according to the N sets of prediction parameters;
wherein both of the first parameter and the second parameter are constants, and wherein the control component is configured to:
obtain the N sets of prediction parameters according to the M first results, the M target read voltages, the preset function model, the first parameter and the second parameter; or
wherein i is equal to 2, wherein the first parameter is a variable, and the second parameter is a constant, and wherein the control component is configured to:
obtain the N sets of prediction parameters and the first parameter according to the M first results, the M target read voltages, the preset function model and the second parameter; or
wherein i is equal to 3, wherein both of the first parameter and the second parameter are variables, and wherein the control component is configured to:
obtain the N sets of prediction parameters, the first parameter and the second parameter according to the M first results, the M target read voltages, and the preset function model.