IP Library Patent Application 18821923
Patent Application
App. No. 18/821,923

Window-Integrated Charge-Mode Digital-to-Analog Converter for Arbitrary Waveform Generator

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Quick Facts
Patent No.
US None
App. No.
18/821,923
Abstract

A digital-to-analog converter circuit that creates an analog waveform from an input digital waveform. Operating the circuit comprises using the input digital waveform to 1) operate a charge control switch to set a charge time period, 2) operate a discharge control switch to set a discharge time period, 3) set a charge current magnitude using a charge gain, and 4) set a discharge current magnitude using a discharge gain. A charge source electrically charges a load capacitor during the charge time period (i.e., the charge mode). A discharge source electrically discharges the load capacitor during the discharge time period (i.e., the discharge mode). A circuit output transmits the analog waveform defined by the charge mode and the discharge mode. A charge current magnitude greater than the discharge current magnitude produces an upward-sloping analog waveform. A charge current magnitude less than the discharge current magnitude produces a downward-sloping analog waveform.

Claims (39)

1 . A digital-to-analog converter circuit comprising:

a charging controlled input configured to operate, using an input digital waveform, a charge control switch to set a charge time period;

a discharging controlled input configured to operate, using the input digital waveform, a discharge control switch to set a discharge time period;

a charge source configured to electrically charge a load capacitor during the charge time period, to define a charge mode;

a discharge source configured to electrically discharge the load capacitor during the discharge time period, to define a discharge mode; and

a circuit output configured to transmit an analog waveform defined at least in part by the charge mode and the discharge mode.

2 . The digital-to-analog converter circuit according to claim 1 , wherein the charge time period and the discharge time period are simultaneous within an operation window, to define a charge integration window.

3 . The digital-to-analog converter circuit according to claim 1 , wherein the charging controlled input is further configured to create a charging control signal from the input digital waveform and to transmit the charging control signal to operate the charge control switch.

4 . The digital-to-analog converter circuit according to claim 3 , wherein the charging control signal is characterized by an On state to operate the charge control switch to enable the charge mode.

5 . The digital-to-analog converter circuit according to claim 3 , wherein the charging control signal is characterized by an Off state to operate the charge control switch to disable the charge mode.

6 . The digital-to-analog converter circuit according to claim 1 , wherein the discharging controlled input is further configured create a discharging control signal from the input digital waveform and to transmit the discharging control signal to operate the charge control switch.

7 . The digital-to-analog converter circuit according to claim 6 , wherein the discharging control signal is characterized by an On state to operate the discharge control switch to enable the discharge mode.

8 . The digital-to-analog converter circuit according to claim 6 , wherein the discharging control signal is characterized by an Off state to operate the discharge control switch to disable the discharge mode.

9 . A method of operating a digital-to-analog converter circuit comprising a charging controlled input, a charge control switch, a discharging controlled input, a discharge control switch, a charge source, a discharge source, and a load capacitor; the method comprising:

receiving, using the charging controlled input and the discharging controlled input, an input digital waveform;

operating, using the charging controlled input, the charge control switch to set a charge time period based on the input digital waveform;

operating, using the discharging controlled input, the discharge control switch to set a discharge time period based on the input digital waveform;

electrically charging, using the charge source, the load capacitor during the charge time period, to define a charge mode;

electrically discharging, using the discharge source, the load capacitor during the discharge time period, to define a discharge mode; and

transmitting, using the circuit output, an analog waveform defined at least in part by the charge mode and the discharge mode.

10 . The method according to claim 9 , wherein the charge time period and the discharge time period are simultaneous within an operation window, to define a charge integration window.

11 . The method according to claim 9 , further comprising creating, using the charging controlled input, a charging control signal from the input digital waveform; and transmitting, using the charging controlled input, the charging control signal to the charge control switch.

12 . The method according to claim 11 , further comprising operating, using the charging control signal characterized by an On state, the charge control switch to enable the charge mode.

13 . The method according to claim 11 , further comprising operating, using the charging control signal characterized by an Off state, the charge control switch to disable the charge mode.

14 . The method according to claim 9 , further comprising creating, using the discharging controlled input, a discharging control signal from the input digital waveform; and transmitting, using the discharging controlled input, the discharging control signal to the charge control switch.

15 . The method according to claim 14 , further comprising operating, using the discharging control signal characterized by an On state, the discharge control switch to enable the discharge mode.

16 . The method according to claim 14 , further comprising operating, using the discharging control signal characterized by an Off state, the discharge control switch to disable the discharge mode.

17 . A method of operating an analog waveform generation system having a digital-to-analog converter circuit comprising a charging controlled input, a charge control switch, a discharging controlled input, a discharge control switch, a charge source having a charge gain, a discharge source having a discharge gain, and a circuit output; the method comprising:

transmitting an input digital waveform to the digital-to-analog converter circuit;

operating, using the charging controlled input, the charge control switch to set a charge time period based on the input digital waveform;

operating, using the discharging controlled input, the discharge control switch to set a discharge time period equal to the charge time period based on the input digital waveform;

operating, using the charge gain, the charge source to set a charge current magnitude based on the input digital waveform;

operating, using the discharge gain, the discharge source to set a discharge current magnitude based on the input digital waveform;

electrically supplying, using the charge source, a charging current during the charge time period, to define a charge mode;

electrically supplying, using the discharge source, a discharging current during the discharge time period, to define a discharge mode; and

transmitting, using the circuit output, an analog waveform defined at least in part by the charge mode and the discharge mode.

18 . The method according to claim 17 , wherein the charge current magnitude is greater than the discharge current magnitude and the analog waveform is characterized by an upward-sloping substantially linear segment.

19 . The method according to claim 17 , wherein the charge current magnitude is less than the discharge current magnitude and the analog waveform is characterized by a downward-sloping substantially linear segment.

20 . The method according to claim 17 , wherein the digital-to-analog converter circuit further comprises a cryogenic Application-Specific Integrated Circuit (ASIC).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2025
From: FERMI RESEARCH ALLIANCE, LLC
To: FERMI FORWARD DISCOVERY GROUP, LLC
Reel/Frame 069716/0452 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2024
From: LI, SHAORUI
To: FERMI RESEARCH ALLIANCE, LLC
Reel/Frame 069449/0666 →