IP Library Granted Patent US 12,396,250
Granted Patent B2
US 12,396,250 · App. 18/872,218 · Granted Aug 19, 2025

Vertical IGBT with complementary channel for hole extraction

Inventor: Gaurav Gupta (Lenzburg, CH)
Assignee: HITACHI ENERGY LTD
H10D84/82H10D64/117H10D84/0123
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Quick Facts
Patent No.
US 12,396,250
App. No.
18/872,218
Granted
Aug 19, 2025
Kind
B2
Abstract

The semiconductor device comprises a semiconductor body with a top side, a main electrode on the top side and a gate electrode. The semiconductor body comprises a drift layer of a first conductivity type, a first base region of a second conductivity type, a second base region of the first conductivity type, a first contact region of the first conductivity type and a second contact region of the second conductivity type. The second base region has a greater doping concentration than the drift layer. The first contact region adjoins the first base region and the top side. The second contact region adjoins the second base region and the top side. The main electrode is in electrical contact with the first and the second contact region. In a first lateral direction, at least a portion of the gate electrode is arranged between the first contact region and the second contact region.

Claims (55)

1. A bipolar semiconductor device, comprising:

a semiconductor body with a top side and a back side,

a main electrode on the top side,

a further main electrode on the back side, and

a gate electrode, wherein

the semiconductor body comprises

a drift layer of a first conductivity type,

a first base region of a second conductivity type arranged vertically between the drift layer and the top side,

a second base region of the first conductivity type arranged vertically between the drift layer and the top side, the second base region having a greater doping concentration than the drift layer and adjoining the drift layer,

a first contact region of the first conductivity type, the first contact region adjoining the first base region and the top side,

a second contact region of the second conductivity type, the second contact region adjoining the second base region and the top side,

the main electrode is in electrical contact with the first contact region and the second contact region,

in a first lateral direction, at least a portion of the gate electrode is arranged between the first contact region and the second contact region as well as between the first base region and the second base region,

a thickness of an insulating material between the first contact region and/or the first base region and the gate electrode is greater than a thickness of an insulating material between the second contact region and/or the second base region and the gate electrode.

2. The bipolar semiconductor device according to claim 1 , wherein

the semiconductor device is configured such that, by setting the electrical potential of the gate electrode,

either a zone of the first base region is inverted by means of the gate electrode and a current flow of first-type charge carriers between the drift layer and the first contact region through this zone is enabled, or

a zone of the second base region is inverted by means of the gate electrode and a current flow of second-type charge carriers between the drift layer and the second contact region through this zone is enabled.

3. The bipolar semiconductor device according to claim 1 , wherein

the semiconductor device is a planar device with the gate electrode arranged on the top side.

4. The bipolar semiconductor device according to claim 1 , wherein

the semiconductor device is a trench device with the gate electrode being arranged in an active trench extending from the top side in a vertical direction into the semiconductor body.

5. The bipolar semiconductor device according to claim 4 , further comprising

at least one dummy trench arranged next to the active trench and spaced from the active trench in the first lateral direction, wherein

the dummy trench is filled with an electrically conductive material which is electrically connected to the main electrode.

6. The bipolar semiconductor device according to claim 1 , wherein

an enhancement region of the first conductivity type is arranged vertically between the first base region and the drift layer,

the enhancement region has a greater doping concentration than the drift layer.

7. The bipolar semiconductor device according to claim 1 , wherein

a third base region being of the second conductivity type is arranged next to the second base region in the first lateral direction so that the second base region is arranged between the first and the third base region in the first lateral direction.

8. The bipolar semiconductor device according to claim 7 , wherein

the semiconductor device is a trench device with the gate electrode being arranged in an active trench extending from the top side in a vertical direction into the semiconductor body,

the third base region extends from the top side into the semiconductor body and deeper into the semiconductor body than the active trench.

9. The bipolar semiconductor device according to claim 1 , wherein the main electrode is not in direct electrical contact with the second base region.

10. The bipolar semiconductor device according to claim 2 , further comprising

a further gate electrode spaced from the gate electrode in the first lateral direction, wherein

the second base region is arranged between the gate electrode and the further gate electrode in the first lateral direction,

the semiconductor device is configured such that, by setting the electrical potential of the further gate electrode, a zone of the second base region is inverted by means of the further gate electrode, said zone being located at a side of the second base region opposite to the side of the second base region at which the zone of the second base region is inverted by means of the gate electrode and thereby provides a current path at this opposite side.

11. The bipolar semiconductor device according to claim 1 , wherein

the first and/or the second contact regions are elongated regions extending in a second lateral direction being oblique to the first lateral direction.

12. The bipolar semiconductor device according to claim 1 , further comprising

several first contact regions adjoining the top side and the first base region and being in electrical contact with the main electrode, wherein the first contact regions are separated and spaced from each other in a second lateral direction being oblique to the first lateral direction and/or

several second contact regions adjoining the top side and the second base region and being in electrical contact with the main electrode, wherein the second contact regions are separated and spaced from each other in a second lateral direction being oblique to the first lateral direction.

13. The bipolar semiconductor device according to claim 1 , wherein the semiconductor device is an IGBT.

14. A method for producing a bipolar semiconductor device, comprising:

providing a semiconductor body with a top side, a back side and a drift layer of a first conductivity type,

producing

a first base region being of a second conductivity type so that the first base region lies vertically between the drift layer and the top side,

a second base region being of the first conductivity type so that the second base region lies vertically between the drift layer and the top side, wherein the second base region has a greater doping concentration than the drift layer and adjoins the drift layer,

a first contact region being of the first conductivity type so that the first contact region adjoins the first base region and the top side,

a second contact region being of the second conductivity type so that the second contact region adjoins the second base region as well as the top side,

applying a main electrode onto the top side and establishing an electrical contact between the main electrode and the first contact region as well as between the main electrode and the second contact region,

applying a further main electrode onto the back side,

forming a gate electrode so that, in the end, at least a portion of the gate electrode lies between the first contact region and the second contact region as well as between the first base region and the second base region in a first lateral direction,

a thickness of an insulating material between the first contact region and/or the first base region and the gate electrode is greater than a thickness of an insulating material between the second contact region and/or the second base region and the gate electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2024
From: GUPTA, GAURAV
To: HITACHI ENERGY SWITZERLAND AG
Reel/Frame 069502/0475 →
MERGER Recorded Dec 5, 2024
From: HITACHI ENERGY SWITZERLAND AG
To: HITACHI ENERGY LTD
Reel/Frame 069502/0481 →
Continuity (1)
Related Publication 20250169165A1 · May 22, 2025
References Cited (14)
US 20090008674A1 · Udrea · 2009 [cited by applicant]
US 20130026537A1 · Rahimo et al. · 2013 [cited by applicant]
US 20180226398A1 · Ogura et al. · 2018 [cited by applicant]
US 20190148532A1 · Naito · 2019 [cited by applicant]
US 20190312101A1 · Sakurai · 2019 [cited by examiner]
CN 113964180A · 2022 [cited by applicant]
JP 2008053378A · 2008 [cited by applicant]
JP 2009188290A · 2009 [cited by applicant]
JP 2018125486A · 2018 [cited by applicant]
Jun Huang et al., “Simulation Study of a Low on-State Voltage Superjunction IGBT With Self-Biased PMOS,” IEEE Transactions on Electron Devices, vol. 66, No. 7, Jul. 2019, 5 pages. [cited by applicant]
Jie Wei et al., “Low Switching Loss and EMI Noise IGBT With Self-Adaptive Hole-Extracting Path”, IEEE Transactions on Electron Devices, vol. 68, No. 5, May 2021, 5 pages. [cited by applicant]
N. Luther-King et al., “Performance of a trench PMOS gated, planar, 1.2 kV Clustered Insulated Gate Bipolar Transistor in NPT technology,” 2009 IEEE, 4 pages. [cited by applicant]
European Patent Office, International Preliminary Report On Patentability received in PCT/EP2022/066367, mailed May 16, 2024, 16 pages. [cited by applicant]
European Patent Office, International Search Report and Written Opinion of the International Searching Authority received in PCT/EP2022/066367, mailed Jan. 24, 2023, 19 pages. [cited by applicant]