HYBRID TEST READ SCHEME USING IN-NAND PARTIAL CHECKSUM
A memory device and method for a hybrid test read scheme using two thresholds based on in-NAND partial checksum and normal test read. The memory device includes: at least one super block including memory blocks; a control circuit to perform a first test read on a codeword sequence; and a partial checksum calculator to calculate a partial checksum on a syndrome sequence based on the codeword sequence and a subset matrix. The control circuit compares the partial checksum with first and second thresholds. When the partial checksum is less than the first threshold, it is determined that the codeword sequence is clean. When the partial checksum is greater than the second threshold, it is determined that the codeword sequence is noisy. When the partial checksum is in between the first and second thresholds, a second test read by a controller is performed on the codeword sequence.
1 . A memory device in a memory system, comprising:
one or more super blocks, each super block including a plurality of memory blocks;
a control circuit in the memory device and configured to perform a first test read on a codeword sequence from the plurality of memory blocks; and
a partial checksum calculator in the memory device and configured to calculate a partial checksum on a syndrome sequence based on the codeword sequence and a subset matrix derived from a parity check matrix,
wherein the control circuit is configured to:
compare the partial checksum with first and second thresholds;
when it is determined that the partial checksum is less than the first threshold, determine that the codeword sequence is clean;
when it is determined that the partial checksum is greater than the second threshold, determine that the codeword sequence is noisy; and
when it is determined that the partial checksum is in between the first threshold and the second threshold, perform by a controller of the memory system a second test read on the codeword sequence to determine a number of failed bit counts for the codeword sequence read from the plurality of memory blocks.
2 . The memory device of claim 1 , wherein the control circuit is further configured to send the noisy codeword sequence to the controller for decoding and error correcting.
3 . The memory device of claim 1 , wherein the second threshold is greater than or equal to the first threshold.
4 . The memory device of claim 1 , wherein the second test read includes multiple test reads in a background operation on a super block.
5 . The memory device of claim 4 , wherein the multiple test reads are performed based on a tracked read count of the super block.
6 . The memory device of claim 1 , wherein the second test read includes multiple test reads in a foreground operation on all pages of multiple super blocks, and each test read is performed on each page.
7 . A method for operating a memory device in a memory system, the method comprising:
performing a first test read on a codeword sequence from a plurality of memory blocks in one or more super blocks;
calculating a partial checksum on a syndrome sequence based on the codeword sequence and a subset matrix derived from a parity check matrix;
comparing the partial checksum with first and second thresholds;
when it is determined that the partial checksum is less than the first threshold, determining that the codeword sequence is clean;
when it is determined that the partial checksum is greater than the second threshold, determining that the codeword sequence is noisy; and
when it is determined that the partial checksum is in between the first threshold and the second threshold, performing a second test read by a controller of the memory system on the codeword sequence to determine a number of failed bit counts for the codeword sequence read from the plurality of memory blocks.
8 . The method of claim 7 , further comprising sending the noisy codeword sequence to the controller for decoding and error correcting.
9 . The method of claim 7 , wherein the second threshold is greater than or equal to the first threshold.
10 . The method of claim 7 , wherein the second test read includes multiple test reads in a background operation on a super block.
11 . The method of claim 10 , wherein the multiple test reads are performed based on a tracked read count of the super block.
12 . The method of claim 7 , wherein the second test read includes multiple test reads in a foreground operation on all pages of multiple super blocks, and each test read is performed on each page.
13 . A method for operating a memory device in a memory system, the method comprising:
performing a test read on a codeword sequence from a plurality of memory blocks in one or more super blocks;
calculating a partial checksum on a syndrome sequence based on the codeword sequence and a subset matrix derived from a parity check matrix;
comparing the partial checksum with first and second thresholds;
when it is determined that the partial checksum is less than the first threshold, determining that the codeword sequence is clean;
when it is determined that the partial checksum is greater than the second threshold, determining that the codeword sequence is noisy; and
when it is determined that the partial checksum is in between the first threshold and the second threshold, generating status information of the partial checksum on the plurality of memory blocks, and determining that the codeword sequence is clean or noisy based on the status information.
14 . The method of claim 13 , further comprising: generating the status information for each page of the plurality of memory blocks included in a super block.
15 . The method of claim 14 , wherein the generating of the status information includes:
generating the status information with a first value when it is determined that the partial checksum for a first page is in between the first threshold and the second threshold,
generating the status information with the first value when it is determined that the partial checksum for a second page is in between the first threshold and the second threshold, the second page is read subsequent to the first page in a particular memory block, and
determining that the codeword sequence is clean when it is determined that the partial checksum for the first and second pages is in between the first threshold and the second threshold.
16 . The method of claim 13 , further comprising: sending a noisy codeword sequence to a controller of the memory system for decoding and error correcting.
17 . The method of claim 13 , wherein the second threshold is greater than or equal to the first threshold.
18 . The method of claim 13 , wherein the second test read includes multiple test reads in a background operation on a super block.
19 . The method of claim 18 , wherein the multiple test reads are performed based on a tracked read count of the super block.
20 . The method of claim 13 , wherein the second test read includes multiple test reads in a foreground operation on all pages of multiple super blocks, and each test read is performed on each page.