Semiconductor device
A control circuit provided in a semiconductor device receives an input data signal during a selection period in which a selection signal has a predetermined level in synchronization with a clock signal and performs a corresponding operation corresponding to the input data signal during the selection period or after the selection period. The control circuit holds an error flag indicating whether a specific error has occurred, outputs, during a part of the selection period, a response signal corresponding to the input data signal from a data output terminal and outputs, during another part of the selection period, an error flag signal corresponding to the value of the error flag from the data output terminal.
1 . A semiconductor device configured
to include: a selection input terminal configured to receive a selection signal; a clock input terminal; a data input terminal; and a data output terminal, and
to be capable of performing serial communication, the semiconductor device comprising
a control circuit configured
to receive, as an input data signal, during a selection period in which the selection signal has a predetermined level, a signal applied to the data input terminal in synchronization with a clock signal applied to the clock input terminal, and
to perform a corresponding operation corresponding to the input data signal during the selection period or after the selection period,
wherein the control circuit
holds an error flag indicating whether a specific error has occurred,
outputs, during a part of the selection period, a response signal corresponding to the input data signal from the data output terminal and
outputs, during another part of the selection period, an error flag signal corresponding to a value of the error flag from the data output terminal,
wherein the control circuit includes a memory and is capable of performing, as the corresponding operation, a write operation on the memory in response to the reception of the input data signal,
the input data signal when the write operation is performed includes:
an address signal indicating a write target address in the memory; and
a write data signal indicating write data to be written to the write target address,
the control circuit writes, during the write operation, the write data to the write target address in the memory,
when the write operation is performed, the selection period includes an error flag output period and a response signal output period,
the control circuit outputs the error flag signal from the data output terminal during the error flag output period, and outputs the response signal from the data output terminal during the response signal output period, and
the response signal when the write operation is performed includes the address signal and the write data signal which have been received and a signal of an error detection code.
2 . The semiconductor device according to claim 1 ,
wherein the control circuit
outputs the error flag signal from the data output terminal in response to transition of a level of the selection signal from another level to the predetermined level, and
thereafter outputs the response signal from the data output terminal.
3 . The semiconductor device according to claim 2 ,
wherein the clock signal for a plurality of cycles is applied to the clock input terminal during the selection period, and
the control circuit
outputs, during the selection period, the error flag signal from the data output terminal in a first cycle for the clock signal, and
outputs the response signal from the data output terminal in second and subsequent cycles for the clock signal.
4 . The semiconductor device according to claim 1 ,
wherein the control circuit
outputs, during the selection period, the error flag signal from the data output terminal after completion of the output of the response signal from the data output terminal, or
outputs, during the selection period, the error flag signal after a part of the response signal is output from the data output terminal and
thereafter outputs a remaining part of the response signal from the data output terminal.
5 . The semiconductor device according to claim 1 ,
wherein the control circuit includes an error detection circuit configured to detect whether a plurality of types of errors have occurred, and
one or more errors of the plurality of types of errors correspond to the specific error.
6 . A semiconductor device configured
to include: a selection input terminal configured to receive a selection signal; a clock input terminal; a data input terminal; and a data output terminal, and
to be capable of performing serial communication, the semiconductor device comprising
a control circuit configured
to receive, as an input data signal, during a selection period in which the selection signal has a predetermined level, a signal applied to the data input terminal in synchronization with a clock signal applied to the clock input terminal, and
to perform a corresponding operation corresponding to the input data signal during the selection period or after the selection period,
wherein the control circuit
holds an error flag indicating whether a specific error has occurred,
outputs, during a part of the selection period, a response signal corresponding to the input data signal from the data output terminal and
outputs, during another part of the selection period, an error flag signal corresponding to a value of the error flag from the data output terminal,
wherein the control circuit includes a memory and is capable of performing, as the corresponding operation, a read operation on the memory in response to the reception of the input data signal,
the input data signal when the read operation is performed includes an address signal indicating a read target address in the memory,
when the read operation is performed, the selection period includes an error flag output period and a response signal output period and
when the read operation is performed in response to the reception of the input data signal, the control circuit:
outputs the error flag signal from the data output terminal during the error flag output period, and
outputs the response signal including a signal of storage data in the read target address from the data output terminal during the response signal output period,
when the read operation is performed, the response signal output period includes a first response signal output period and a second response signal output period,
the control circuit:
outputs, as a first response signal, the signal of the storage data in the read target address from the data output terminal during the first response signal output period; and
outputs a second response signal from the data output terminal during the second response signal output period, and
the second response signal includes the address signal which has been received and a signal of an error detection code.
7 . The semiconductor device according to claim 6 ,
wherein the control circuit
outputs the error flag signal from the data output terminal in response to transition of a level of the selection signal from another level to the predetermined level, and
thereafter outputs the response signal from the data output terminal.
8 . The semiconductor device according to claim 7 ,
wherein the clock signal for a plurality of cycles is applied to the clock input terminal during the selection period, and
the control circuit
outputs, during the selection period, the error flag signal from the data output terminal in a first cycle for the clock signal, and
outputs the response signal from the data output terminal in second and subsequent cycles for the clock signal.
9 . The semiconductor device according to claim 6 ,
wherein the control circuit
outputs, during the selection period, the error flag signal from the data output terminal after completion of the output of the response signal from the data output terminal, or
outputs, during the selection period, the error flag signal after a part of the response signal is output from the data output terminal and
thereafter outputs a remaining part of the response signal from the data output terminal.
10 . The semiconductor device according to claim 6 ,
wherein the control circuit includes an error detection circuit configured to detect whether a plurality of types of errors have occurred, and
one or more errors of the plurality of types of errors correspond to the specific error.
11 . A semiconductor device configured
to include: a selection input terminal configured to receive a selection signal; a clock input terminal; a data input terminal; and a data output terminal, and
to be capable of performing serial communication, the semiconductor device comprising
a control circuit configured
to receive, as an input data signal, during a selection period in which the selection signal has a predetermined level, a signal applied to the data input terminal in synchronization with a clock signal applied to the clock input terminal, and
to perform a corresponding operation corresponding to the input data signal during the selection period or after the selection period,
wherein the control circuit
holds an error flag indicating whether a specific error has occurred,
outputs, during a part of the selection period, a response signal corresponding to the input data signal from the data output terminal and
outputs, during another part of the selection period, an error flag signal corresponding to a value of the error flag from the data output terminal,
wherein the control circuit is operated in a first setting state or a second setting state based on setting information, and
the control circuit:
outputs, in the first setting state, the error flag signal from the data output terminal during a non-selection period in which the selection signal has another level different from the predetermined level; and
stops, in the second setting state, the output of the error flag signal from the data output terminal during the non-selection period.
12 . The semiconductor device according to claim 11 ,
wherein the control circuit
outputs the error flag signal from the data output terminal in response to transition of a level of the selection signal from another level to the predetermined level, and
thereafter outputs the response signal from the data output terminal.
13 . The semiconductor device according to claim 12 ,
wherein the clock signal for a plurality of cycles is applied to the clock input terminal during the selection period, and
the control circuit
outputs, during the selection period, the error flag signal from the data output terminal in a first cycle for the clock signal, and
outputs the response signal from the data output terminal in second and subsequent cycles for the clock signal.
14 . The semiconductor device according to claim 11 ,
wherein the control circuit
outputs, during the selection period, the error flag signal from the data output terminal after completion of the output of the response signal from the data output terminal, or
outputs, during the selection period, the error flag signal after a part of the response signal is output from the data output terminal and
thereafter outputs a remaining part of the response signal from the data output terminal.
15 . The semiconductor device according to claim 11 ,
wherein the control circuit includes an error detection circuit configured to detect whether a plurality of types of errors have occurred, and
one or more errors of the plurality of types of errors correspond to the specific error.