Robust single event upset (SEU) tolerant high-performance flip-flop
Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.
1 . An integrated circuit, comprising:
a master-slave latch circuit comprising:
master latch circuitry comprising a data input configured to receive data and a data output configured to output the data;
slave latch circuitry; and
a first tristate driver comprising a data input configured to receive the data from the data output of the master latch circuitry, and a data output coupled to a first data input of the slave latch circuitry;
wherein the first tristate driver comprises:
an inverter circuit configured to invert the data output of the master latch circuitry;
a pull-up transistor configured to provide a supply voltage to the inverter circuit based on a first clock; and
a pull-down transistor configured to provide a reference voltage to the inverter circuit based on an inverse of the first clock; and
wherein the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the data output of the master latch circuitry.
2 . The integrated circuit of claim 1 , wherein:
a logic state of the data output of the first tristate driver is based on the data output of the master latch circuitry when a first clock is at a first state, and is based on a state of a storage node of the slave latch circuitry when the first clock is at a second state.
3 . The integrated circuit of claim 1 , further comprising:
a second tristate driver comprising a data input coupled to the data output of the master latch circuitry, and a data output coupled to a second data input of the slave latch circuitry;
wherein the second tristate driver is configured to inhibit charge transfer from the second data input of the slave latch circuitry to the data output of the master latch circuitry.
4 . The integrated circuit of claim 3 , wherein the second tristate driver comprises:
a second inverter circuit configured to invert the data output of the master latch circuitry;
a second pull-up transistor configured to provide the supply voltage to the second inverter circuit based on a second clock; and
a second pull-down transistor configured to provide the reference voltage to the second inverter circuit based on an inverse of the second clock.
5 . The integrated circuit of claim 4 , further comprising:
a first clock circuit configured to generate the first clock and the inverse of the first clock based on an input clock; and
a second clock circuit configured to generate the second clock and the inverse of the second clock based on the input clock;
wherein the first clock circuit comprises a first driver transistor;
wherein the second clock circuit comprises a second driver transistor;
wherein a fanout of the first clock circuit is greater than a fanout of the second clock circuit; and
wherein a size of the first driver transistor is greater than a size of the second driver transistor.
6 . The integrated circuit of claim 1 , wherein:
the first tristate driver is further configured to inhibit charge transfer associated with logic state transitions in the slave latch circuitry.
7 . The integrated circuit of claim 1 , wherein:
the master-slave latch circuit is configured to mitigate singe event upsets.
8 . The integrated circuit of claim 1 , wherein:
the master-slave latch circuit is configured as a single event upset (SEU) tolerant flip-flop.
9 . The integrated circuit of claim 1 , wherein the master-slave latch circuit comprises a dual double interlocked storage cell (DICE).
10 . The integrated circuit of claim 1 , wherein the first tristate driver is further configured to increase a static noise margin of an internal latch node of the master latch circuitry.
11 . An integrated circuit, comprising:
a master-slave latch circuit comprising master latch circuitry, slave latch circuitry, and a first tristate driver having a data input coupled to a data output of the master latch circuitry and a data output coupled to a first data input of the slave latch circuitry;
wherein the first tristate driver comprises:
a first inverter circuit configured to invert the data output of the master latch circuitry;
a first pull-up transistor configured to provide a supply voltage to the first inverter circuit based on a first clock; and
a first pull-down transistor configured to provide a reference voltage to the first inverter circuit based on an inverse of the first clock; and
wherein the master-slave latch circuit is configured as a single event upset (SEU) tolerant flip-flop
wherein the first tristate driver is configured to increase a static noise margin of an internal latch node of the master latch circuitry.
12 . The integrated circuit of claim 11 , further comprising:
a second tristate driver having a data input coupled to the data output of the master latch circuitry and a data output coupled to a second data input of the slave latch circuitry, wherein the second tristate driver comprises:
a second inverter circuit configured to invert the data output of the master latch circuitry;
a second pull-up transistor configured to provide the supply voltage to the second inverter circuit based on a second clock; and
a second pull-down transistor configured to provide the reference voltage to the second inverter circuit based on an inverse of the second clock.
13 . The integrated circuit of claim 12 , further comprising:
a first clock circuit configured to generate the first clock and the inverse of the first clock based on an input clock; and
a second clock circuit configured to generate the second clock and the inverse of the second clock based on the input clock;
wherein the first clock circuit comprises a first driver transistor;
wherein the second clock circuit comprises a second driver transistor; and
wherein a fanout of the first clock circuit is greater than a fanout of the second clock circuit; and
wherein a size of the first driver transistor is greater than a size of the second driver transistor.
14 . The integrated circuit of claim 11 , wherein the first tristate driver is configured to increase a static noise margin of an internal latch node of the master latch circuitry master.
15 . An integrated circuit device, comprising:
a field-programmable gate array (FPGA), comprising random access memory (RAM) circuitry, wherein the RAM circuitry comprises a dual double interlocked storage cell (DICE), and wherein the DICE comprises master latch circuitry comprising a data input configured to receive data and a data output configured to output the data, slave latch circuitry, and a first tristate driver having a data input coupled to the data output of the master latch circuitry and a data output coupled to a first data input of the slave latch circuitry;
wherein the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the data output of the master latch circuitry.
16 . The integrated circuit device of claim 15 , wherein:
a logic state of the data output of the first tristate driver is based on the data output of the master latch circuitry when a first clock is at a first state, and is based on a state of a storage node of the slave latch circuitry when the first clock is at a second state.
17 . The integrated circuit device of claim 15 , further comprising:
a second tristate driver having a data input coupled to the data output of the master latch circuitry and a data output coupled to a second data input of the slave latch circuitry;
wherein the first tristate driver comprises,
a first inverter circuit configured to invert the data output of the master latch circuitry;
a first pull-up transistor configured to provide a supply voltage to the first inverter circuit based on a first clock; and
a first pull-down transistor configured to provide a reference voltage to the first inverter circuit based on an inverse of the first clock; and
wherein the second tristate driver comprises:
a second inverter circuit configured to invert the data output of the master latch circuitry;
a second pull-up transistor configured to provide the supply voltage to the second inverter circuit based on a second clock; and
a second pull-down transistor configured to provide the reference voltage to the second inverter circuit based on an inverse of the second clock.
18 . The integrated circuit device of claim 17 , further comprising:
a first clock circuit configured to generate the first clock and the inverse of the first clock based on an input clock; and
a second clock circuit configured to generate the second clock and the inverse of the second clock based on the input clock;
wherein the first clock circuit comprises a first driver transistor;
wherein the second clock circuit comprises a second driver transistor;
wherein a fanout of the first clock circuit is greater than a fanout of the second clock circuit; and
wherein a size of the first driver transistor is greater than a size of the second driver transistor.
19 . The integrated circuit device of claim 15 , wherein the first tristate driver is further configured to increase a static noise margin of an internal latch node of the master latch circuitry.