IP Library Granted Patent US 12,547,574
Granted Patent B2
US 12,547,574 · App. 18/891,841 · Granted Feb 10, 2026

I/O carrier and backplane for industrial process control systems

Inventors: Richard Mann (Austin, TX); Charles Eastberg (Round Rock, TX); Scott Slade (Round Rock, TX)
Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
G06F13/409
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,547,574
App. No.
18/891,841
Granted
Feb 10, 2026
Kind
B2
Abstract

An I/O device is configured to couple a plurality of process control field devices to a process controller controlling a process in an industrial process plant. The I/O device includes a backplane and a plurality of electronic marshalling component (EMC) slots. The EMC slots are each configured to receive a respective EMC and to receive either of (i) a first-type EMC associated with a first communication protocol or (ii) second-type EMC associated with a second communication protocol. The I/O device also includes I/O processor module slots, each communicatively coupled, via the backplane, to each of the EMC slots and to each of a first one or more connectors and a second one or more connectors in each of the EMC slots. The I/O device further includes communication ports, each communicatively coupled to the I/O processor module slots via the backplane.

Claims (30)

1 . An I/O device configured to couple a plurality of process control field devices to a process controller controlling a process in an industrial process plant, the I/O device comprising:

a backplane;

a plurality of electronic marshalling component (EMC) slots, each of the EMC slots configured to receive a respective EMC, and each of the EMC slots configured to receive either of (i) a first-type EMC associated with a first communication protocol and an associated discrete terminal block by coupling to a first one or more connectors or (ii) second-type EMC associated with a second communication protocol and having an integrated terminal block by coupling to a second one or more connectors;

one or more I/O processor module slots, each of the one or more I/O processor module slots communicatively coupled, via the backplane, to each of the plurality of EMC slots and to each of the first one or more connectors and the second one or more connectors in each of the plurality of EMC slots; and

one or more communication ports, each communicatively coupled to each of the one or more I/O processor module slots via the backplane, and each configured to communicatively couple the each of the one or more I/O processor module slots to the process controller.

2 . An I/O device according to claim 1 , wherein each of the EMC slots comprises:

a card-edge connector disposed in the slot to physically and communicatively couple to a second-type EMC; and

a first plurality of conventional connectors disposed in the slot and configured to communicatively couple to field wiring of the plurality of process control field devices; and

a second plurality of conventional connectors disposed in the slot and configured to communicatively couple to a first-type EMC.

3 . An I/O device according to claim 1 , wherein the first-type EMC is a conventional EMC.

4 . An I/O device according to claim 1 , wherein the second-type EMC is an advanced physical layer (APL) EMC.

5 . An I/O device according to claim 1 , further comprising a plurality of APL EMCs installed in a first subset of the plurality EMC slots and a plurality of conventional EMCs installed in a second subset of the plurality EMC slots, each of the conventional EMCs and the APL EMCs including a memory and a processor for performing communications.

6 . An I/O device according to claim 2 , wherein the backplane is configured to communicate, for each EMC slot, signals between the first plurality of conventional connectors and a subset of the second plurality of conventional connectors.

7 . An I/O device according to claim 2 , wherein the backplane is configured to communicatively couple each EMC slot to each of the I/O processor module slots.

8 . An I/O device according to claim 7 , wherein the backplane is configured to communicatively couple, for each EMC slot, one or more connections on the card-edge connector and one or more of the second plurality of conventional connectors to each of the I/O process module slots.

9 . An I/O device according to claim 2 , further comprising a plurality of slot adapters, each of the slot adapters configured to (i) cover a respective card-edge connector in one of the EMC slots and (ii) facilitate seating and latching of a respective first-type EMC.

10 . An I/O device according to claim 2 , wherein each of the EMC slots further comprises a terminal latch, the terminal latch configured to physically engage with a first-type EMC and to facilitate seating and latching of the first-type EMC.

11 . An I/O device according to claim 1 , wherein the plurality of EMC slots comprises a first array of EMC slots and a second array of EMC slots.

12 . An I/O device according to claim 1 , wherein the plurality of EMC slots comprises 24 EMC slots.

13 . An I/O device according to claim 1 , wherein each of the EMC slots is configured such that, when the EMC slot receives a second-type EMC, the second-type EMC covers and does not communicatively or physically engage with connectors configured to communicate signals to and/or from a first-type EMC.

14 . An I/O device according to claim 1 , wherein each of the EMC slots is configured such that, when the EMC slot receives a first-type EMC, the first-type EMC does not cover, communicatively engage, or physically engage with a connector configured to couple to a second-type EMC.

15 . An I/O device according to claim 1 , wherein a first array of EMC slots is disposed on a left side of the I/O device, a second array of EMC slots is disposed on a right side of the I/O device, and the one or more I/O processor slots and the one or more communication ports are disposed in a central portion of the I/O device between the left side and the right side.

16 . An I/O device according to claim 1 , wherein each of the plurality of EMC slots is configured to facilitate linear insertion of a second-type EMC, and to facilitate pivoting insertion of a first-type EMC.

17 . An I/O device according to claim 1 , wherein the each of the plurality of EMC slots has a same length dimension and a same width dimension as a first-type EMC slot configured to receive a terminal block for a first-type EMC.

18 . An I/O device according to claim 17 , wherein each of the EMC slots comprises:

a set of pogo terminals disposed in the slot to communicatively couple to a second-type EMC;

a first plurality of conventional connectors disposed in the slot and configured to communicatively couple to field wiring of the plurality of process control field devices; and

a second plurality of conventional connectors disposed in the slot and configured to communicatively couple to a first-type EMC.

19 . An I/O device according to claim 1 , wherein the one or more communication ports are disposed within a body of the I/O device such that the one or more communication ports couple to communication media from a bottom surface of the I/O device, and wherein a contiguous airflow path is created extending from the bottom surface of the body of the I/O device, through a body of each of the one or more communication ports, and through the body of the I/O device.

20 . An electronic marshalling component (EMC) configured to communicatively and physically couple to any one of the plurality of EMC slots of the I/O device of claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2024
From: MANN, RICHARD; EASTBERG, CHARLES; SLADE, SCOTT
To: FISHER-ROSEMOUNT SYSTEMS, INC.
Reel/Frame 068653/0368 →
Continuity (2)
Provisional Application 63542002 · Oct 2, 2023
Related Publication 20250110911A1 · Apr 3, 2025
References Cited (22)
US 7684875B2 · Jundt et al. · 2010 [cited by applicant]
US 8332567B2 · Burr et al. · 2012 [cited by applicant]
US 8762618B2 · Burr et al. · 2014 [cited by applicant]
US 8977851B2 · Neitzel et al. · 2015 [cited by applicant]
US 9083548B2 · Holmes et al. · 2015 [cited by applicant]
US 9495313B2 · Burr et al. · 2016 [cited by applicant]
US 12424527B2 · Olson · 2025 [cited by examiner]
US 20050195975A1 · Kawakita · 2005 [cited by examiner]
US 20120265867A1 · Boucher · 2012 [cited by examiner]
US 20140351319A1 · Lee · 2014 [cited by examiner]
US 20150120972A1 · Tanimura et al. · 2015 [cited by applicant]
US 20170344445A1 · Vanderah et al. · 2017 [cited by applicant]
US 20170344451A1 · Vanderah et al. · 2017 [cited by applicant]
US 20180113830A1 · Sherriff et al. · 2018 [cited by applicant]
US 20190089461A1 · Sun · 2019 [cited by examiner]
US 20210081346A1 · Nixon et al. · 2021 [cited by applicant]
US 20230111740A1 · Law et al. · 2023 [cited by applicant]
US 20250110463A1 · Law · 2025 [cited by examiner]
US 20250110911A1 · Mann · 2025 [cited by examiner]
CN 111104262A · 2020 [cited by applicant]
International Search Report and Written Opinion for Application No. PCT/US2024/047974, dated Dec. 23, 2024. [cited by applicant]
International Search Report and Written Opinion for Application No. PCT/US2024/047970, dated Dec. 20, 2024. [cited by applicant]