IP Library › Granted Patent US 12,535,915
Granted Patent B2
US 12,535,915 · App. 18/892,844 · Granted Jan 27, 2026

Driver, display touch panel, and controller for stopping and resuming operation of a gate driver

Inventors: Yasuaki Iwase (Kameyama, JP); Seijirou Gyouten (Kameyama, JP); Satoshi Horiuchi (Kameyama, JP); Shinji Matsubara (Kameyama, JP)
Assignee: Sharp Display Technology Corporation
G06F3/04184G09G3/3677G09G3/3266G09G2310/0267G09G2310/08
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Quick Facts
Patent No.
US 12,535,915
App. No.
18/892,844
Granted
Jan 27, 2026
Kind
B2
Abstract

A drive circuit includes a plurality of stages and configured to supply a drive signal to a scanning signal line group in response to input of a plurality of clock signals. The drive circuit includes a plurality of unit circuits respectively constituting the plurality of stages, the plurality of unit circuits being configured to output the drive signal, a latch circuit provided in parallel with the plurality of unit circuits, and a connection circuit connected to an output node of the latch circuit.

Claims (37)

1 . A drive circuit including a plurality of stages and configured to supply a drive signal to a scanning signal line group in response to input of a plurality of clock signals, the drive circuit comprising:

a plurality of unit circuits forming, respectively, the plurality of stages, the plurality of unit circuits being configured to output the drive signal;

a latch circuit provided in parallel with the plurality of unit circuits; and

a connection circuit connected to an output node of the latch circuit,

wherein the latch circuit:

receives, as a first set signal, an input of a first output signal from a first unit circuit, among the plurality of unit circuits, that forms a first stage, among the plurality of stages,

outputs a latch circuit output signal to the connection circuit via the output node when a first control signal that resumes an operation of the drive circuit is input after the first set signal is input, and

receives, as a first reset signal, an input of a second output signal from a second unit circuit, among the plurality of unit circuits, that forms a second stage among stages of the plurality of stages that are subsequent to the first stage, and

the connection circuit includes:

a reset circuit configured to reset the first unit circuit and a third unit circuit, among the plurality of unit circuits, that forms a stage, among the plurality of stages, that is next to the first stage in response to an input of a second control signal that stops the operation of the drive circuit, and

a set circuit configured to supply the latch circuit output signal to the third unit circuit, as a second set signal.

2 . The drive circuit according to claim 1 ,

wherein the third unit circuit includes:

an internal node,

a first transistor configured to charge the internal node in response to the input of the first output signal received from the first unit circuit,

a second transistor configured to output the drive signal to any one scanning signal line of the scanning signal line group when any one of the plurality of clock signals is input in a state in which the internal node is charged, and

a third transistor configured to discharge the internal node in response to an input of a second reset signal received from a fourth unit circuit forming a stage, among the plurality of stages, that is subsequent to the stage formed by the third unit circuit,

the reset circuit and the set circuit are connected to the internal node,

the reset circuit discharges the internal node in response to receiving the input of the second control signal, and

the set circuit charges the internal node in response to receiving an input of the latch circuit output signal.

3 . The drive circuit according to claim 1 ,

wherein the second stage configured by the second unit circuit is next to the first stage, and

the third unit circuit also serves as the second unit circuit.

4 . The drive circuit according to claim 1 ,

wherein the second stage formed by the second unit circuit is subsequent to a stage, among the plurality of stages, that is formed by the third unit circuit.

5 . A display device comprising:

the drive circuit according to claim 1 ; and

a display in which the scanning signal line group is disposed.

6 . An in-cell touch panel device comprising:

the drive circuit according to claim 1 ; and

an in-cell touch panel provided with the scanning signal line group, the in-cell touch panel being configured to detect a touch of a pointer within a period of time in which the operation of the drive circuit is stopped.

7 . A control device for a drive circuit, the control device being configured to supply, to the drive circuit according to claim 1 , the plurality of clock signals, the first control signal, and the second control signal,

wherein the drive circuit further comprises:

a plurality of latch circuits, including the latch circuit, provided in parallel with the plurality of unit circuits, and

a plurality of connection circuits, including the connection circuit, connected to output nodes of the plurality of latch circuits, respectively, wherein the control device for the drive circuit:

determines an operation connection circuit to be operated by one or more of the plurality of connection circuits, and

supplies the second control signal to the operation connection circuit, without supplying the second control signal to any connection circuit, among the plurality of connection circuits, other than the operation connection circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2024
From: ZHU, DEYAN; JAMES, JEREMY
To: FOUR DROBOTICS CORPORATION
Reel/Frame 068948/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2024
From: IWASE, YASUAKI; GYOUTEN, SEIJIROU; HORIUCHI, SATOSHI; MATSUBARA, SHINJI
To: SHARP DISPLAY TECHNOLOGY CORPORATION
Reel/Frame 068661/0801 →
Priority Claims (1)
JP 2023-177896 · Oct 13, 2023 · national
Continuity (1)
Related Publication 20250123716A1 · Apr 17, 2025
References Cited (3)
US 20180196563A1 · Iwase et al. · 2018 [cited by applicant]
US 20230229249A1 · Sasaki · 2023 [cited by examiner]
WO 2017006815A1 · 2017 [cited by applicant]