IP Library › Granted Patent US 12,684,122
Granted Patent B2
US 12,684,122 · App. 18/906,260 · Granted Jul 14, 2026

Encoder and decoder, encoding method and decoding method for versatile spatial partitioning of coded pictures

Inventors: Valeri George (Berlin, DE); Tobias Hinz (Berlin, DE); Jackie Ma (Berlin, DE); Yago Sánchez De La Fuente (Berlin, DE); Robert Skupin (Berlin, DE); Thomas Schierl (Berlin, DE); Jens Brandenburg (Berlin, DE); Christian Lehmann (Berlin, DE); Adam Wieckowski (Berlin, DE); Heiko Schwarz (Berlin, DE); Detlev Marpe (Berlin, DE); Thomas Wiegand (Berlin, DE)
Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
H04N19/119H04N19/172H04N19/1883H04N19/46
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Quick Facts
Patent No.
US 12,684,122
App. No.
18/906,260
Filed
Oct 4, 2024
Granted
Jul 14, 2026
Kind
B2
Art Unit
2481
USPC
375/240.02
Abstract

A video decoder for decoding an encoded video signal including encoded picture data and indication data of a picture of a video to reconstruct the picture of the video is provided. The video decoder includes an interface configured for receiving the encoded video signal, and a data decoder configured for reconstructing the picture of the video by decoding the encoded picture data using the indication data. The picture is partitioned into a plurality of coding areas. One or more coding areas of the plurality of coding areas include two or more coding tree units of the plurality of coding tree units, wherein each coding area of the one or more coding areas which includes two or more coding tree units exhibits a coding order for the two or more coding tree units of the coding area.

Claims (31)

1 . An apparatus for decoding a picture from a bitstream, the apparatus comprising:

a memory; and

one or more processors coupled to the memory, the one or more processors configured to perform operations comprising:

deriving, from the bitstream, one or more tile rows and one or more tile columns to obtain a tile comprising a sequence of coding tree units (CTUs) that covers a rectangular region of the picture;

decoding or inferring, from the bitstream, a tile partitioning syntax element indicating a presence of tile partitioning information in the bitstream; and

deriving, from the tile partitioning information in the bitstream, a syntax element specifying heights of a plurality of rectangular regions within the tile, wherein the heights of the plurality of rectangular regions are specified as a number of CTU rows.

2 . The apparatus of claim 1 , wherein the tile partitioning information further comprises a second syntax element indicating a number of the plurality of rectangular regions within the tile.

3 . The apparatus of claim 1 , wherein the tile partitioning information is included in a picture parameter set.

4 . A method for decoding a picture from a bitstream, comprising:

deriving, from the bitstream, one or more tile rows and one or more tile columns to obtain a tile comprising a sequence of coding tree units (CTUs) that covers a rectangular region of the picture;

decoding or inferring, from the bitstream, a tile partitioning syntax element indicating a presence of tile partitioning information in the bitstream; and

deriving, from the tile partitioning information in the bitstream, a syntax element specifying heights of a plurality of rectangular regions within the tile, wherein the heights of the plurality of rectangular regions are specified as a number of CTU rows.

5 . The method of claim 4 , wherein the tile partitioning information further comprises a second syntax element indicating a number of the plurality of rectangular regions within the tile.

6 . The method of claim 4 , wherein the tile partitioning information is included in a picture parameter set.

7 . A non-transitory computer-readable medium including instructions which, when executed by one or more processors, cause the one or more processors to perform the method of claim 4 .

8 . A method for encoding a picture into a bitstream, comprising:

partitioning the picture with one or more tile rows and one or more tile columns to obtain a tile comprising a sequence of coding tree units (CTUs) that covers a rectangular region of the picture;

partitioning the tile with a plurality of horizontal boundaries to obtain a plurality of rectangular regions within the tile; and

encoding, into the bitstream, tile partitioning information comprising a syntax element specifying heights of the plurality of rectangular regions, wherein the heights of the plurality of rectangular regions are specified as a number of CTU rows.

9 . The method of claim 8 , wherein the tile partitioning information further comprises a second syntax element indicating a number of the plurality of rectangular regions within the tile.

10 . The method of claim 8 , wherein the tile partitioning information is included in a picture parameter set.

11 . The method of claim 8 , further comprising:

encoding, into the bitstream, a flag syntax element indicating a presence of the tile partitioning information.

12 . An apparatus for encoding a picture into a bitstream, the apparatus comprising:

a memory; and

one or more processors coupled to the memory, the one or more processors configured to perform the method of claim 8 .

13 . The apparatus of claim 12 , wherein the tile partitioning information further comprises a second syntax element indicating a number of the plurality of rectangular regions within the tile.

14 . The apparatus of claim 12 , wherein the tile partitioning information is included in a picture parameter set.

15 . The apparatus of claim 12 , the one or more processors configured further configured to perform operations comprising:

encoding, into the bitstream, a flag syntax element indicating a presence of the tile partitioning information.

16 . A non-transitory computer-readable medium including instructions which, when executed by one or more processors, cause the one or more processors to perform the method of claim 8 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2025
From: GEORGE, VALERI; HINZ, TOBIAS; MA, JACKIE; SÁNCHEZ DE LA FUENTE, YAGO; SKUPIN, ROBERT; SCHIERL, THOMAS; BRANDENBURG, JENS; LEHMANN, CHRISTIAN; WIECKOWSKI, ADAM; SCHWARZ, HEIKO; MARPE, DETLEV; WIEGAND, THOMAS
To: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Reel/Frame 071588/0818 →
Priority Claims (1)
EP 18182554 · Jul 9, 2018 · regional
Continuity (5)
Continuation 18449562 · Aug 14, 2023
Continuation 17719249 · Apr 12, 2022
Continuation 17140560 · Jan 4, 2021
Continuation PCTEP2019068429 · Jul 9, 2019
Related Publication 20250030853A1 · Jan 23, 2025
References Cited (39)
US 8855201B2 · Kim · 2014 [cited by examiner]
US 10542294B2 · Huang · 2020 [cited by applicant]
US 20150016520A1 · Rapaka · 2015 [cited by applicant]
US 20150201501A1 · Chi · 2015 [cited by applicant]
US 20180048895A1 · Jeon · 2018 [cited by applicant]
EP 3185553A1 · 2017 [cited by applicant]
EP 3509301B1 · 2023 [cited by applicant]
JP 2014030187A · 2014 [cited by applicant]
JP 2016103707A · 2016 [cited by applicant]
KR 20170136411A · 2017 [cited by applicant]
WO 2012121420A1 · 2012 [cited by applicant]
WO 2015083575A1 · 2015 [cited by applicant]
WO 2017108638A1 · 2017 [cited by applicant]
WO 2017115207A1 · 2017 [cited by applicant]
WO 2017157249A1 · 2017 [cited by applicant]
WO 2017209394A1 · 2017 [cited by applicant]
WO 2018044087A1 · 2018 [cited by applicant]
WO 2019185815A1 · 2019 [cited by applicant]
WO 2019185821A1 · 2019 [cited by applicant]
WO 2020185883A1 · 2020 [cited by applicant]
Atsuro Ichigaya et al., “Coding efficiency improvement of 64x64 CU on HEVC [in Japanese with the English title)”, Proceedings of FIT 2015 (The 14th Forum on Information Technology), 3, pp. 285 to 289, Aug. 24, 2015. [cited by applicant]
Benjamin Bross, et al., “Versatile Video Coding (Draft 5)”, Document: JVET-N1001-v10, [online], Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, JVET-N1001 (version 10), Jul. 2, 2019, p… [cited by applicant]
Benjamin Bross, et al., “Versatile Video Coding (Draft 6)”, Document: JVET-O2001-vE, [online], Joint Video Experts Team (JVET) of ITU-T SG16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, JVET-P1024 (version 1), Oct. 9, 2019, pp. … [cited by applicant]
Examination Report received in Japanese Application No. 2021-500701, dated May 17, 2022 (English translation). [cited by applicant]
Examination Report received in Taiwanese Application No. 110135275, dated Apr. 13, 2022 (English translation). [cited by applicant]
H.264/AVC Textbook, Revised Third Edition [in Japanese, title translated] supervised by Sakae Okubo, first edition, Jan. 1, 2009, Impress R D, pp. 177 to 180 and 199 to 204. [cited by applicant]
International Search Report and Written Opinion, dated Nov. 22, 2019, PCT Application No. PCT/EP2019/068429, filed Jul. 9, 2019. [cited by applicant]
ISO/IEC, ITU-T. High efficiency video coding. ITU-T Recommendation H.265 | ISO/IEC 23008 10 (HEVC) edition 2; Oct. 2014; pp. 1-540. [cited by applicant]
Office Action dated Jan. 5, 2023, U.S. Appl. No. 17/719,249, filed Apr. 12, 2022. [cited by applicant]
Office Action dated Nov. 12, 2021, U.S. Appl. No. 17/140,560, filed Jan. 4, 2021. [cited by applicant]
Oh, H.M., et al.; “MCTS extraction with implicit slice reordering;” Joint Collaborative Team on Video Coding of ISO/IEC JTC1/SC29/WG11 and ITU-T SG.16; Oct. 2017; pp. 1-3. [cited by applicant]
R. Skupin, et al., “Tile-based region-of-interest signaling with sub-picture SEI messages”, Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and 1SO/IEC JTC 1/SC 29/WG 11, Oct. 1, 2012, JCTVC-K0218 … [cited by applicant]
Recommendation ITU-T H.264 (Jan. 2012), ITU-T, Jan. 13, 2012, pp. 5 to 14, 42 to 46, 76 to 81 and 115 to 118. [cited by applicant]
Shiodera, Taichiro, et al., “Block Based Extra/Inter-Polating Prediction for Intra Coding”, IEEE International Conference on Image Processing, San Antonio, TX, USA, Sep. 16, 2007-Oct. 19, 2007, pp. VI-445-VI-448. [cited by applicant]
Skupin, R., et al.; “AHG 12: Sub-bitstream extraction/merging friendly slice address signaling;” The Joint Video Exploration Team of ISO/IEC JTC1/SC29/WG11 and ITU-T SG.16; Sep. 2018; pp. 1-5. [cited by applicant]
Tokumichi Murakami et al. (eds.), “High efficiency video coding technology HEVC/H.265 and its application [in Japanese, title translated]”, first edition, Feb. 25, 2013, Ohmsha, Ltd., pp. 14 to 18 and 82 to 92. [cited by applicant]
Wang, Ye-Kui, et al., “Tile Groups”, Joint Collaborative Team on Video Coding (JCT-VG) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WVG11, 7th Meeting: Geneva, CH, Nov. 21-30, 2011. [cited by applicant]
Ye-Kui Wang, et al., “AHG12: Signalling for tile and brick partitioning”, Document: JVET-N0857-v1, [online], Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, JVET-N0857 (version 2), Mar… [cited by applicant]
ISO/IEC, ITU-T. High efficiency video coding. ITU-T Recommendation H.265 | ISO/IEC 23008 10 (HEVC), edition 1; Apr. 2013; pp. 1-317. [cited by applicant]