CACHE STRUCTURE AND UTILIZATION
Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.
1 - 22 . (canceled)
23 . An apparatus comprising:
one or more processors including a graphics processing unit (GPU);
a memory for storage of data for processing by the one or more processors; and
a cache to cache data from the memory for use by the one or more processors;
wherein the one or more processors are to:
monitor operation of the cache,
identify one or more cache lines for pre-eviction of data from the cache based at least in part on the monitoring of the cache, and
pre-evict data from the one or more cache lines of the cache.
24 . The apparatus of claim 23 , wherein monitoring operations of the cache includes monitoring the cache for eviction patterns for data in the cache.
25 . The apparatus of claim 24 , wherein the one or more cache lines are identified based at least in part on a detected eviction pattern for the cache.
26 . The apparatus of claim 23 , wherein the pre-eviction of the data from the one or more cache lines is performed prior to allocation of the one or more cache lines for fetched data.
27 . The apparatus of claim 23 , wherein the pre-eviction of the data from the one or more cache lines is performed prior to a read miss for the cache.
28 . The apparatus of claim 23 , wherein the one or more processors are further to:
receive a read request resulting in a miss in the cache; and
fetch data for the read request from the memory and store the fetched data in the one or more cache lines.
29 . The apparatus of claim 28 , wherein the storage of the fetched data in the one or more cache lines is performed without additional eviction of data from the one or more cache lines.
30 . One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
monitoring operation of a cache for one or more processors including a graphics processing unit (GPU) in a computing system;
identifying one or more cache lines for pre-eviction of data from the cache based at least in part on the monitoring of the cache; and
pre-evicting data from the one or more cache lines of the cache.
31 . The one or more computer-readable storage mediums of claim 30 , wherein monitoring operations of the cache includes monitoring the cache for eviction patterns for data in the cache.
32 . The one or more computer-readable storage mediums of claim 31 , wherein identifying the one or more cache lines includes identifying the one or more cache lines based at least in part on a detected eviction pattern for the cache.
33 . The one or more computer-readable storage mediums of claim 30 , wherein the pre-eviction of the data from the one or more cache lines is performed prior to allocation of the one or more cache lines for fetched data.
34 . The one or more computer-readable storage mediums of claim 30 , wherein the pre-eviction of the data from the one or more cache lines is performed prior to a read miss for the cache.
35 . The one or more computer-readable storage mediums of claim 30 , wherein the executable computer program instructions further include instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
receiving a read request resulting in a miss in the cache; and
fetching data for the read request from a memory in the computing system and storing the fetched data in the one or more cache lines.
36 . The one or more computer-readable storage mediums of claim 35 , wherein storing the fetched data in the one or more cache lines is performed without additional eviction of data from the one or more cache lines.
37 . A method comprising:
monitoring operation of a cache for one or more processors including a graphics processing unit (GPU) in a computing system, wherein monitoring operations of the cache includes monitoring the cache for eviction patterns for data in the cache;
identifying one or more cache lines for pre-eviction of data from the cache based at least in part on the monitoring of the cache; and
pre-evicting data from the one or more cache lines of the cache.
38 . The method of claim 37 , wherein identifying the one or more cache lines includes identifying the one or more cache lines based at least in part on a detected eviction pattern for the cache.
39 . The method of claim 37 , wherein the pre-eviction of the data from the one or more cache lines is performed prior to allocation of the one or more cache lines for fetched data.
40 . The method of claim 37 , wherein the pre-eviction of the data from the one or more cache lines is performed prior to a read miss for the cache.
41 . The method of claim 37 , further comprising:
receiving a read request resulting in a miss in the cache; and
fetching data for the read request from a memory in the computing system and storing the fetched data in the one or more cache lines.
42 . The method of claim 41 , wherein storing the fetched data in the one or more cache lines is performed without additional eviction of data from the one or more cache lines.