VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
A caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.
1 . A system comprising:
a first sub-cache;
a second sub-cache; and
a cache controller,
wherein:
the second sub-cache includes a set of lines and a set of line type bits, wherein each line type bit of the set of line type bits corresponds to a respective line of the set of lines;
each line of the set of lines is configured to operate in a first manner to store data associated with a write-miss or a second manner to store data associated with an eviction of a cache entry from the first sub-cache; and
the cache controller is configured to determine, based on whether a line of the set of lines operates in the first manner or the second manner, whether to store a first indication in a line type bit of the set of line type bits corresponding to the line to indicate that data stored in the line is associated with a write-miss or a second indication to indicate that the data is associated with an eviction of a cache entry from the first sub-cache.
2 . The system of claim 1 , wherein the second sub-cache comprises a tag random access memory (RAM) configured to store a respective memory address for each line of a first subset of the set of lines associated with a write-miss.
3 . The system of claim 1 , wherein the second sub-cache comprises a byte-enable memory configured to store a respective byte-enable mask for each line of the set of lines associated with a write-miss.
4 . The system of claim 3 , wherein the byte-enable memory includes memory positions corresponding with each line of the set of lines of the second sub-cache.
5 . The system of claim 1 , wherein the set of line type bits is stored in a memory configured to store modified, exclusive, shared, and invalid (MESI) states of the set of lines in the second sub-cache.
6 . The system of claim 1 , wherein the first sub-cache is a n-way set associative cache, and wherein the second sub-cache is a fully associative cache.
7 . The system of claim 1 , wherein the first sub-cache is a main cache, and wherein the second sub-cache is a victim cache in parallel with the main cache.
8 . The system of claim 1 , wherein the cache controller is configured to:
receive a write request; and
determine whether the write request corresponds to a miss in the first sub-cache and, in parallel, determine whether the write request corresponds to a miss in the second sub-cache.
9 . A method, comprising:
receiving a write memory request specifying to write first data to a caching system, wherein the caching system includes a first sub-cache and a second sub-cache, and wherein the second sub-cache includes a set of lines and a set of line type bits, each line type bit of the set of line type bits corresponding to a respective line of the set of lines;
determining whether the write memory request corresponds to a write miss in the first sub-cache;
determining whether the write memory request corresponds to a write miss in the second sub-cache; and
determining, based on whether the write memory request corresponds to a write miss in the first sub-cache and the second sub-cache, whether to store a first indication in a first line type bit of the set of line type bits corresponding to a first line of the set of lines to indicate that data stored in the first line is associated with a write-miss.
10 . The method of claim 9 , further comprising storing a memory address associated with the first data in a tag random access memory (RAM).
11 . The method of claim 9 , further comprising storing byte enable logic associated with the first data in a byte-enable memory.
12 . The method of claim 11 , further comprising storing memory positions corresponding with each line of the set of lines in the byte-enable memory.
13 . The method of claim 9 , wherein the first line type bit is stored in a memory that stores modified, exclusive, shared, and invalid (MESI) states of entries in the second sub-cache.
14 . The method of claim 9 , wherein the first sub-cache is a n-way set associative cache and wherein the second sub-cache is a fully associative cache.
15 . The method of claim 9 , wherein the first sub-cache is a main cache, and wherein the second sub-cache is a victim cache in parallel with the main cache.
16 . The method of claim 9 , determining whether to store the first indication in the first line type bit comprises:
determining, based on that the write memory request corresponds to a write miss in the first sub-cache and the second sub-cache, to store the first indication in first the line type bit to indicate that the data stored in the first line is associated with a write-miss.
17 . The method of claim 9 , comprising:
storing data associated with an eviction from the first sub-cache in the first line; and
determining to store a second indication in the first line type bit to indicate that the date stored in the first line is associated with an eviction from the first sub-cache.
18 . A device, comprising:
a processor configured to provide a write memory request for a memory address; and
a caching system comprising:
a first sub-cache; and
a second sub-cache including a set of lines and a set of line type bits, each line type bit of the set of line type bits corresponding to a respective line of the set of lines,
wherein the caching system is configured to:
determine whether the memory address is cached in the first sub-cache of the caching system;
determine whether the memory address is cached in the second sub-cache of the caching system; and
determine, based on whether the memory address is cached in the first sub-cache and the second sub-cache, whether to store a first indication in a first line type bit of the set of line type bits corresponding to a first line of the set of lines to indicate that data stored in the first line is associated with a write-miss.
19 . The device of claim 18 , wherein the caching system is configured to:
determine, based on that the memory address is not cached in the first sub-cache or the second sub-cache, to store the first indication in the first line type bit to indicate that the data stored in the first line is associated with a write-miss.
20 . The device of claim 18 , wherein the caching system is configured to:
store data associated with an eviction from the first sub-cache in the first line; and
determine to store a second indication in the first line type bit to indicate that the date stored in the first line is associated with an eviction from the first sub-cache.