APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
1 . A device comprising:
a Peripheral Component Interconnect Express (PCIe) circuit;
a set of registers;
a set of time source circuits that includes the PCIe circuit;
a set of endpoint circuits that includes the PCIe circuit;
a router coupled between the set of time source circuits and the set of endpoint circuits, wherein:
each of the set of time source circuits is configured to provide a respective time domain signal;
each of the set of endpoint circuits is configured to receive, from the router, a respective time domain signal; and
the router is configured to selectively couple each of the set of endpoint circuits to at least one of the set of time source circuits.
2 . The device of claim 1 , wherein the PCIe circuit is configured to:
in a first mode:
receive a first timing signal;
determine the respective time domain signal of the PCIe circuit based on the first timing signal; and
provide the respective time domain signal to the router;
in a second mode:
receive the respective time domain signal of a first time source circuit of the set of time source circuits via the router; and
provide a second timing signal based on the respective time domain signal of the first time source circuit to a PCIe endpoint.
3 . The device of claim 2 , wherein the first mode is a PCIe endpoint mode and the second mode is a PCIE root complex mode.
4 . The device of claim 2 , wherein the determining of the respective time domain signal includes recovering a Precision Time Means (PTM) clock signal from the first timing signal.
5 . The device of claim 1 , wherein the router is configured to provide the respective time domain signal provided by the PCIe circuit as an application domain time domain signal.
6 . The device of claim 1 , wherein the router is configured to provide the respective time domain signal provided by the PCIe circuit as a communication domain time domain signal.
7 . The device of claim 1 , wherein the set of time source circuits includes at least one of: a global positioning satellite time source or an industrial Ethernet time source.
8 . The device of claim 1 , wherein the router is configured to:
generate a bit mask correlating each of the set of each of the set of endpoint circuits to at least one of the set of time source circuits;
store the bit mask in the set of registers; and
perform the selective coupling of each of the set of endpoint circuits to at least one of the set of time source circuits based on the bit mask.
9 . The device of claim 1 , wherein the router is configured to:
determine a failure associated with the respective time domain signal of a first time source circuit of the set of time source circuits; and
based on the failure, provide the respective time domain signal of a second time source circuit of the set of time source circuits to a first endpoint circuit of the set of endpoint circuits.
10 . A device comprising:
a set of time source circuits;
a set of endpoint circuits;
a router circuit coupled to the set of time source circuits and the set of endpoint circuits; and
a first circuit coupled to the router circuit and configured to:
in a first mode, provide a first time domain signal to the router circuit; and
in a second mode:
receive a second time domain signal from the router circuit; and
provide a timing signal based on the second time domain signal.
11 . The device of claim 10 , wherein the first circuit is a Peripheral Component Interconnect Express (PCIe) interface circuit.
12 . The device of claim 11 , wherein the first mode is a Peripheral Component Interconnect Express (PCIe) endpoint mode and the second mode is a PCIE root complex mode.
13 . The device of claim 10 , wherein:
the timing signal is a first timing signal; and
the providing of the first time domain signal by the first circuit includes:
receiving a second timing signal;
recovering a Precision Time Means (PTM) clock signal from the second timing signal; and
providing the first time domain signal based on the PTM clock signal.
14 . The device of claim 10 , wherein the router circuit is configured to provide the first time domain signal as an application domain time domain signal.
15 . The device of claim 10 , wherein the router circuit is configured to provide the first time domain signal as a communication domain time domain signal.
16 . The device of claim 10 , wherein the router circuit is configured to:
determine a failure associated with a respective time domain signal of a first time source circuit of the set of time source circuits; and
based on the failure, provide a respective time domain signal of a second time source circuit of the set of time source circuits to a first endpoint circuit of the set of endpoint circuits.
17 . A method comprising:
providing, by a Peripheral Component Interconnect Express (PCIe) circuit, a first time domain signal to a router;
providing, by the router, the first time domain signal to an endpoint circuit;
providing, by the router, a second time domain signal to the PCIe circuit; and
providing, by the PCIe circuit, a timing signal that is based on the second time domain signal to a PCIe endpoint.
18 . The method of claim 17 , wherein:
the timing signal is a first timing signal; and
the providing of the first time domain signal includes:
receiving a second timing signal;
recovering a Precision Time Means (PTM) clock signal from the second timing signal; and
determining the first time domain signal based on the PTM clock signal.
19 . The method of claim 17 , wherein the providing of the first time domain signal provides the first time domain signal as a application domain time domain signal.
20 . The method of claim 17 , wherein the providing of the first time domain signal provides the first time domain signal as a communication domain time domain signal.