IP Library › Patent Application 18917954
Patent Application
App. No. 18/917,954

DEEP LEARNING BASED ITERATIVE VOLTAGE THRESHOLD ESTIMATION FOR NAND FLASH MEMORY

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Patent No.
US None
App. No.
18/917,954
Abstract

A memory system and associated method for calculating a voltage threshold for reading data from the memory system. The memory system including a memory device including multiple pages in a memory region and a controller coupled to the memory device. The controller is configured to: perform at least one read operation on the memory device including reading of the multiple pages in a memory region of the memory device to obtain program voltage state distributions across the multiple pages; generate a synthetic model of the program voltage state distributions of the memory device based on the at least one read operation; and calculate from the synthetic model at least one voltage threshold between two of the program voltage state distributions.

Claims (42)

1 . A memory system comprising:

a memory device including multiple pages in a memory region; and

a controller coupled to the memory device, and configured to:

perform at least one read operation on the memory device including reading of the multiple pages in the memory region of the memory device to obtain program voltage state distributions across the multiple pages;

generate a synthetic model of the program voltage state distributions of the memory device based on the at least one read operation; and

calculate from the synthetic model at least one voltage threshold between two of the program voltage state distributions.

2 . The memory system of claim 1 , wherein the synthetic model comprises at least one of a Gaussian Model (GM), an improved Gaussian Model (IGM), a Skew Normal Model (SNM), and non-central T model (NCTM).

3 . The memory system of claim 2 , wherein the controller is further configured to:

vary the synthetic model between iterations which calculate from the synthetic model at least one voltage threshold between two of the program voltage state distributions

4 . The memory system of claim 3 , wherein a first iteration utilizes the GM, a second iteration utilizes the IGM, a third iteration utilizes the SNM, and a fourth iteration utilizes the NCTM.

5 . The memory system of claim 3 , wherein

after at least one of the first, second, and third iterations, the at least one voltage threshold between two of the program voltage state distributions is calculated, and

error detection between each iteration determines whether to perform at least one of the second, third, and fourth iterations.

6 . The memory system of claim 5 , wherein

after the first iteration, a first error detection determines whether to perform the second iteration,

after the second iteration, a second error detection determines whether to perform the third iteration, and

after the third iteration, a third error detection determines whether to perform the fourth iteration.

7 . The memory system of claim 3 , wherein

after at least one of the first, second, and third iterations, a subsequent read operation of the at least one read operation is performed to provide input to a subsequent iteration.

8 . The memory system of claim 1 , wherein the multiple pages include a most significant bit (MSB) page, a center significant bit (CSB) page, and a least significant bit (LSB) page.

9 . The memory system of claim 1 , wherein the controller comprises a neural network which generates the synthetic model and calculates the at least one voltage threshold between two of the program voltage state distributions.

10 . The memory system of claim 1 , wherein the controller is programed with a look up table associating, for the synthetic model, data from the at least one read operation with a volage threshold value for the at least one voltage threshold.

11 . A method for calculating a voltage threshold for reading data from a memory system including a memory device having multiple pages in a memory region and a controller coupled to the memory device, the method comprising:

performing at least one read operation on a memory device including reading of multiple pages in a memory region of the memory device to obtain program voltage state distributions across the multiple pages;

generating a synthetic model of the program voltage state distributions of the memory device based on the at least one read operation; and

calculating from the synthetic model at least one voltage threshold between two of the program voltage state distributions.

12 . The method of claim 11 , wherein the synthetic model comprises at least one of a Gaussian Mode (GM), an improved Gaussian Model (IGM), a Skew Normal Model (SNM), and non-central T model (NCTM) model.

13 . The method of claim 11 , further comprising:

varying the synthetic model between iterations which calculate from the synthetic model at least one voltage threshold between two of the program voltage state distributions.

14 . The method of claim 13 , wherein a first iteration utilizes the GM, a second iteration utilizes the IGM, a third iteration utilizes the SNM, and a fourth iteration utilizes the NCTM.

15 . The method of claim 13 , further comprising:

after at least one of the first, second, and third iterations, calculating the at least one voltage threshold between two of the program voltage state distributions, and

determining with error detection whether to perform at least one of the second, third, and fourth iterations.

16 . The method of claim 15 , further comprising:

after the first iteration, determining by a first error detection whether to perform the second iteration,

after the second iteration, determining by a second error detection whether to perform the third iteration, and

after the third iteration, determining by a third error detection whether to perform the fourth iteration.

17 . The method of claim 13 , further comprising:

after at least one of the first, second, and third iterations, a subsequent read operation of the at least one read operation to provide input to a subsequent iteration.

18 . The method of claim 11 , wherein the performing the at least one read operation on the multiple pages comprises reading a most significant bit (MSB) page, a center significant bit (CSB) page, and a least significant bit (LSB) page.

19 . The method of claim 11 , further comprising generating with a neural network in the controller the synthetic model and calculating with the neural network the at least one voltage threshold between two of the program voltage state distributions.

20 . The method of claim 11 , further comprising providing a look up table in the controller associating, for the synthetic model, data from the at least one read operation with a volage threshold value for the at least one voltage threshold.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2025
From: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
To: SK HYNIX INC.
Reel/Frame 070536/0574 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2024
From: ZHANG, FAN; WANG, HAOBO
To: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
Reel/Frame 068920/0035 →