Image sensors with reduced fixed pattern noise
An imaging system may include an image sensor with an array of pixels arranged in rows and columns. Row driver circuitry may be coupled to the pixels and may address a given row of the pixels based on a row address. Row randomization circuitry may be coupled to the row driver circuitry to dither the row address and therefore randomize the order in which rows of a given column are read out over column lines to sample and hold circuitry that includes a plurality of capacitors for each column. The imaging system may include a multiplexer that de-randomizes the order of the rows after passing through the sample and hold circuitry. Alternatively or additionally, the order in which the plurality of capacitors is used to store the signals from each column may be randomized. In this way, fixed pattern noise in an output image may be reduced or eliminated.
1 . An imaging system, comprising:
an image sensor comprising an array of pixels arranged in rows and columns;
row drivers coupled to the array of pixels, wherein the row drivers are configured to address rows of the array of pixels based on row addresses;
row randomization circuitry coupled to the row drivers, wherein the row randomization circuitry is configured to dither the row addresses; and
column lines coupled to the columns of the array of pixels, wherein signals from the array of pixels are configured to be read out over the column lines based on the dithered row addresses.
2 . The imaging system of claim 1 , further comprising:
column memory banks coupled to the column lines;
a multiplexer coupled to an output of the column memory banks; and
multiplexer control circuitry coupled between the multiplexer and the row randomization circuitry, wherein the multiplexer control circuitry is configured to control the multiplexer to read out the signals based on the dithered row addresses.
3 . The imaging system of claim 2 , further comprising:
sample and hold circuitry coupled to the column lines between the array of pixels and the column memory banks, wherein the sample and hold circuitry comprises at least three capacitors coupled to each of the column lines.
4 . The imaging system of claim 3 , wherein the column memory banks comprise four banks of column memory.
5 . The imaging system of claim 4 , further comprising:
amplifiers coupled to the sample and hold circuitry; and
analog to digital converters coupled to the amplifiers, wherein each of the amplifiers and each of the analog to digital converters are shared between two of the column lines.
6 . The imaging system of claim 1 , wherein the row randomization circuitry comprises a pseudorandom binary sequence generator.
7 . The imaging system of claim 6 , further comprising:
row address adjustment circuitry that is configured to dither the row addresses based on random codes generated by the pseudorandom binary sequence generator.
8 . The imaging system of claim 1 , wherein the row randomization circuitry is configured to randomize an order in which the rows of every set of four rows are read out.
9 . The imaging system of claim 1 , further comprising:
sample and hold circuitry coupled to the column lines, wherein the sample and hold circuitry comprises at least three capacitors configured to store the signals and reset values for each of the column lines; and
sample and hold control circuitry coupled to the sample and hold circuitry, wherein the sample and hold control circuitry is configured to randomize a pattern in which the at least three capacitors are used to store the signals and the reset values on a frame-by-frame basis.
10 . The imaging system of claim 9 , wherein the pattern in which the at least three capacitors are used to store the signals and the reset values is configured to repeat every three rows within a given image frame.
11 . An imaging system, comprising:
an image sensor comprising an array of pixels arranged in rows and columns;
column lines coupled to the columns of the array of pixels, wherein signals from the array of pixels are configured to be read out over the column lines;
sample and hold circuitry coupled to the column lines, wherein the sample and hold circuitry comprises at least three capacitors configured to store the signals and reset values for each of the column lines; and
sample and hold control circuitry coupled to the sample and hold circuitry, wherein the sample and hold circuitry is configured to randomize a pattern in which the at least three capacitors are used to store the signals and the reset values on a frame-by-frame basis.
12 . The imaging system of claim 11 , wherein the sample and hold control circuitry is configured to randomize the pattern in which the at least three capacitors are used to store the signals and the reset values pseudorandomly.
13 . The imaging system of claim 11 , wherein the sample and hold circuitry comprises at least four capacitors configured to store the signals and the reset values for each of the column lines, and the sample and hold circuitry is configured to randomize a pattern in which the at least four capacitors are used to store the signals and the reset values on a frame-by-frame basis.
14 . The imaging system of claim 11 , further comprising:
row driver circuitry coupled to the array of pixels, wherein the row driver circuitry is configured to address rows of the array of pixels based on row addresses; and
row randomization circuitry coupled to the row driver circuitry, wherein the row randomization circuitry is configured to dither the row addresses, and the signals from the array of pixels are configured to be read out over the column lines based on the dithered row addresses.
15 . The imaging system of claim 14 , further comprising:
column memory banks coupled to the column lines;
a multiplexer coupled to an output of the column memory banks; and
multiplexer control circuitry coupled between the multiplexer and the row randomization circuitry, wherein the multiplexer control circuitry is configured to control the multiplexer to read out the signals based on the dithered row addresses.
16 . A method of operating an image sensor comprising an array of pixels arranged in rows and columns, the method comprising:
reading out signals from a given column of the array of pixels with the rows of the given column randomized;
sampling and holding the signals;
storing the signals in column memory banks; and
reading out the signals from the column memory banks with the rows of the given column de-randomized.
17 . The method of claim 16 , further comprising:
with row randomization circuitry, dithering row addresses used to address the rows of the array of pixels to randomize the rows of the given column.
18 . The method of claim 17 , further comprising:
with the row randomization circuitry, controlling the reading out of the signals from the column memory banks.
19 . The method of claim 17 , wherein sampling and holding the signals comprises sampling and holding the signals from the given column and reset values for the given column on at least three capacitors.
20 . The method of claim 19 , further comprising:
randomizing a pattern in which the at least three capacitors are used to store the signals and the reset values on a frame-by-frame basis.