IP Library › Granted Patent US 12,278,218
Granted Patent B2
US 12,278,218 · App. 18/923,340 · Granted Apr 15, 2025

Semiconductor device

Inventors: Takeshi Imamura (Kyoto, JP); Masaaki Hirako (Shiga, JP); Takashi Ohashi (Osaka, JP)
Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
H01L25/072H01L24/29H01L24/32H10D30/668H10D62/117H10D62/126H10D64/252H01L2224/2919H01L2224/32058H01L2224/32137H01L2224/32225H01L2924/13091H01L2924/3511
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Quick Facts
Patent No.
US 12,278,218
App. No.
18/923,340
Granted
Apr 15, 2025
Kind
B2
Abstract

A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer in contact with and connected to an entire back face of the semiconductor layer; and a support bonded to the back face side of the metal layer via a conductive adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a semiconductor chip resulting from excluding the support and the conductive adhesive from the semiconductor device is in a curved shape projecting in a direction away from the support.

Claims (47)

1. A semiconductor device that is a facedown mountable semiconductor device, the semiconductor device comprising:

a semiconductor substrate;

a low-concentration impurity layer that is provided on a front face side of the semiconductor substrate;

a first vertical metal-oxide semiconductor (MOS) transistor that is provided in a first region of a semiconductor layer that is a combination of the semiconductor substrate and the low-concentration impurity layer;

a second vertical MOS transistor that is provided in a second region adjacent to the first region in a plan view of the semiconductor layer;

a first source electrode of the first vertical MOS transistor, the first source electrode being provided on a front face side of the semiconductor layer;

a second source electrode of the second vertical MOS transistor, the second source electrode being provided on the front face side of the semiconductor layer; and

a support that is provided on a back face side of the semiconductor substrate via a conductive adhesive,

wherein in the plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer,

a thickness of the support is greater than a thickness of the semiconductor layer, and

when a semiconductor chip of the semiconductor device excluding the support and the conductive adhesive is seen in a cross-sectional view of the semiconductor device that includes a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, the semiconductor chip is in a curved shape that projects in a direction away from the support.

2. The semiconductor device according to claim 1 ,

wherein in the plan view, the semiconductor layer is in a square shape, and

a thickness of the conductive adhesive immediately below the semiconductor layer in the outer periphery of the semiconductor layer in the plan view is less than a thickness of the conductive adhesive immediately below the semiconductor layer at the center of the semiconductor layer in the plan view.

3. The semiconductor device according to claim 2 ,

wherein in the plan view, the semiconductor layer has an area of at least 6.2 [mm 2 ], and

h≤0.016×S−0.042 is satisfied, where an area and a thickness of the semiconductor layer are denoted by S [mm 2 ] and h [mm], respectively.

4. The semiconductor device according to claim 3 ,

wherein in the plan view, the semiconductor layer has an area of at most 11.5 [mm 2 ], and

h≤0.014×S−0.074 is satisfied.

5. The semiconductor device according to claim 3 , comprising:

a metal layer that is in contact with an entire back face of the semiconductor substrate,

wherein L≥(h+hp)/tan(20 [deg]) is satisfied, where a shortest length of a closest distance from the outer periphery of the semiconductor layer to an outer periphery of the support in the plan view is denoted by L [mm], and a total thickness of the metal layer and the conductive adhesive immediately below the semiconductor layer in a corner portion of the semiconductor layer in the plan view is denoted by hp [mm].

6. The semiconductor device according to claim 3 ,

wherein the support includes a metal.

7. The semiconductor device according to claim 3 , comprising:

a metal layer that is in contact with an entire back face of the semiconductor substrate,

wherein a thickness of the first source electrode is greater than a thickness of the metal layer, and a thickness of the second source electrode is greater than the thickness of the metal layer.

8. The semiconductor device according to claim 3 ,

wherein the conductive adhesive is directly applied to an entire back face of the semiconductor substrate.

9. The semiconductor device according to claim 1 , comprising:

a support metal layer that is located on a front face side of the support and is connected to an area larger in area than the semiconductor substrate in the plan view,

wherein a thickness of the support metal layer is greater than a thickness of the first source electrode, and is greater than a thickness of the second source electrode, and

the support includes an insulating material.

10. The semiconductor device according to claim 3 ,

wherein in the plan view, a front face side of the support includes: a first area that includes a center of the support and does not include an outer periphery of the support; and a second area that surrounds the first area,

in the cross-sectional view, the first area is uniform in height, and the second area includes a portion in which a height of the second area is less than a height of the first area,

in the plan view, an area of the first area is smaller than an area of the semiconductor substrate, and

in the plan view, the semiconductor substrate is disposed to cover an entirety of the first area of the support.

11. The semiconductor device according to claim 10 ,

wherein the second area further includes a portion in which a height of the second area is equal to the height of the first area.

12. The semiconductor device according to claim 3 ,

wherein in the cross-sectional view, the support is in a curved shape that projects in a direction toward the semiconductor chip, and

an amount of curvature of the support is smaller than an amount of curvature of the semiconductor chip.

13. The semiconductor device according to claim 3 ,

wherein in the cross-sectional view, the support is in a curved shape that projects in a direction away from the semiconductor chip, and

an amount of curvature of the support is smaller than an amount of curvature of the semiconductor chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2024
From: IMAMURA, TAKESHI; HIRAKO, MASAAKI; OHASHI, TAKASHI
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 069578/0193 →
Continuity (3)
Continuation PCTJP2024000300 · Jan 10, 2024
Provisional Application 63440617 · Jan 23, 2023
Related Publication 20250046759A1 · Feb 6, 2025
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