Granted Patent B2

US 12,749,979 · App. 18/926,300 · Granted Sep 29, 2026

Inventor: Xiaohui Wu (Shanghai, CN)

Assignee: Shanghai Hanmai Electronic Technology Co., Ltd

H02M3/1584H02M1/0025H02M1/32H02M3/157H02M3/1586

Abstract

Claims (104)

1 . A multi-phase buck converter, comprising:

M converter branches connected in parallel, each of the M converter branches comprising a driving module and a power stage output circuit electrically coupled between the driving module and a voltage output terminal, wherein M is an integer greater than 2; and

a loop error amplifier, configured to compare an output voltage at the voltage output terminal with a reference voltage to generate an output voltage error signal,

wherein the driving module in one of the M converter branches, other than a first converter branch, from a second to an Mth converter branch comprises:

a current information error amplifier, configured to receive, as a first terminal input, a detection voltage across an output inductor of the power stage output circuit in the one of the M converter branches, configured to receive, as a second terminal input, a detection voltage across an output inductor of the power stage output circuit in a previous converter branch, and configured to compare the first terminal input with the second terminal input to generate a current information error signal;

a synchronous ramp voltage generation circuit, configured to generate a synchronous ramp signal based on the output voltage at the voltage output terminal;

a pulse width modulation comparator, configured to superimpose the current information error signal to the output voltage error signal to generate a modulation voltage signal, and compare the modulation voltage signal with the synchronous ramp signal to generate a duty cycle modulation set signal; and

a driving control circuit, configured to generate a driving signal based on the duty cycle modulation set signal, such that the power stage output circuit in the one of the M converter branches outputs the output voltage based on the driving signal;

wherein the driving control circuit in the one of the M converter branches comprises:

an RS flip-flop, configured to generate a duty cycle signal based on the duty cycle modulation set signal; and

a switch driving circuit, configured to generate the driving signal based on the duty cycle signal;

wherein the driving module in the one of the M converter branches further comprises:

an adaptive constant-on-time generation circuit, configured to generate a duty cycle reset signal based on the duty cycle signal and a reference switching frequency of the one of the M converter branches,

wherein the RS flip-flop is configured to generate the duty cycle signal based on the duty cycle modulation set signal and the duty cycle reset signal;

wherein the adaptive constant-on-time generation circuit is configured to:

generate a frequency error signal based on the duty cycle signal and the reference switching frequency:

generate an adaptive on-capacitance voltage signal based on the duty cycle signal; and

generate the duty cycle reset signal based on the frequency error signal and the adaptive on-capacitance voltage signal;

wherein the synchronous ramp voltage generation circuit in the one of the M converter branches is configured to:

generate the synchronous ramp signal based on the output voltage and a voltage at a switch output terminal of the power stage output circuit in the one of the M converter branches,

wherein the output inductor is electrically coupled between the switch output terminal and the voltage output terminal.

2 . The multi-phase buck converter of claim 1 , wherein the power stage output circuit in the one of the M converter branches comprises the output inductor and an RC circuit electrically coupled in parallel with the output inductor, and the RC circuit comprises a filter resistor and a filter capacitor which are electrically coupled in series,

wherein the filter resistor and the filter capacitor are configured to filter a voltage across the output inductor to obtain the detection voltage corresponding to a current flowing through the output inductor.

3 . The multi-phase buck converter of claim 1 , wherein the driving module in the first converter branch of the M converter branches comprises:

a synchronous ramp voltage generation circuit, configured to generate a synchronous ramp signal based on the output voltage at the voltage output terminal;

a pulse width modulation comparator, configured to compare the output voltage error signal with the synchronous ramp signal to generate a duty cycle modulation set signal; and

a driving control circuit, configured to generate a driving signal based on the duty cycle modulation set signal, such that the power stage output circuit in the first converter branch of the M converter branches outputs the output voltage based on the driving signal.

4 . The multi-phase buck converter of claim 1 , wherein the driving module in the first converter branch of the M converter branches comprises:

a current information error amplifier, configured to receive, as a first terminal input, a detection voltage across an output inductor of the power stage output circuit in the first converter branch of the M converter branches, to receive, as a second terminal input, a detection voltage across an output inductor of the power stage output circuit in the Mth converter branch, and to compare the first terminal input with the second terminal input to generate a current information error signal;

a synchronous ramp voltage generation circuit, configured to generate a synchronous ramp signal based on the output voltage at the voltage output terminal;

a pulse width modulation comparator, configured to superimpose the current information error signal to the output voltage error signal to generate a modulation voltage signal, and compare the modulation voltage signal with the synchronous ramp signal to generate a duty cycle modulation set signal; and

a driving control circuit, configured to generate a driving signal based on the duty cycle modulation set signal, such that the power stage output circuit in the first converter branch of the M converter branches outputs the output voltage based on the driving signal.

5 . The multi-phase buck converter of claim 1 , wherein the power stage output circuit in the one of the M converter branches comprises a high-side switch, a low-side switch, the output inductor, a filter resistor, and a filter capacitor,

wherein a source of the high-side switch is electrically coupled to a power supply terminal, a drain of the high-side switch is electrically coupled to a switch output terminal, and a gate of the high-side switch receives the driving signal,

wherein a source of the low-side switch is grounded, a drain of the low-side switch is electrically coupled to the switch output terminal, and a gate of the low-side switch receives the driving signal,

wherein a first terminal of the output inductor is electrically coupled to the switch output terminal, and a second terminal of the output inductor is electrically coupled to the voltage output terminal, and

wherein a first terminal of the filter resistor is electrically coupled to the first terminal of the output inductor, a first terminal of the filter capacitor is electrically coupled to a second terminal of the filter resistor, and a second terminal of the filter capacitor is electrically coupled to the second terminal of the output inductor.

6 . The multi-phase buck converter of claim 1 , wherein the pulse width modulation comparator in the one of the M converter branches comprises:

a first PMOS transistor, wherein a gate of the first PMOS transistor is connected to an output terminal of a corresponding current information error amplifier;

a second PMOS transistor, wherein a gate of the second PMOS transistor is connected to an output terminal of the loop error amplifier, a source of the second PMOS transistor is connected to a source of the first PMOS transistor, and a drain of the second PMOS transistor is connected to a drain of the first PMOS transistor;

a third PMOS transistor, wherein a gate of the third PMOS transistor is connected to an output terminal of a corresponding synchronous ramp voltage generation circuit, and a source of the third PMOS transistor is connected to the source of the second PMOS transistor;

a first comparator, wherein an output terminal of the first comparator outputs the duty cycle modulation set signal;

a first resistor, wherein a first terminal of the first resistor is connected to the drain of the second PMOS transistor and an inverting input terminal of the first comparator, and a second terminal of the first resistor is grounded; and

a second resistor, wherein a first terminal of the second resistor is connected to a drain of the third PMOS transistor and a non-inverting input terminal of the first comparator, and a second terminal of the second resistor is grounded.

7 . The multi-phase buck converter of claim 1 , further comprising a common-mode level generation circuit, wherein the pulse width modulation comparator in the one of the M converter branches comprises:

a fourth PMOS transistor, wherein a gate of the fourth PMOS transistor is connected to an output terminal of the corresponding current information error amplifier;

a fifth PMOS transistor, wherein a gate of the fifth PMOS transistor is connected to an output terminal of the common-mode level generation circuit, a source of the fifth PMOS transistor is connected to a source of the fourth PMOS transistor (NOT SHOWN);

a sixth PMOS transistor, wherein a gate of the sixth PMOS transistor is connected to an output terminal of the loop error amplifier;

a seventh PMOS transistor, wherein a gate of the seventh PMOS transistor is connected to an output terminal of the corresponding synchronous ramp voltage generation circuit, and a source of the seventh PMOS transistor is connected to a source of the sixth PMOS transistor;

a second comparator, wherein an output terminal of the second comparator outputs the duty cycle modulation set signal;

a third resistor, wherein a first terminal of the third resistor is connected to a drain of the fourth PMOS transistor and a drain of the sixth PMOS transistor, and a second terminal of the third resistor is grounded; and

a fourth resistor, wherein a first terminal of the fourth resistor is connected to a drain of the fifth PMOS transistor and a drain of the seventh PMOS transistor, and a second terminal of the fourth resistor is grounded.

8 . The multi-phase buck converter of claim 1 , wherein the current information error amplifier in the one of the M converter branches comprises:

a current information detection amplifier, wherein a non-inverting input terminal of the current information detection amplifier inputs the detection voltage across the output inductor in the previous converter branch, and an inverting input terminal of the current information detection amplifier inputs the detection voltage across the output inductor in the one of the M converter branches;

a first capacitor, wherein a first terminal of the first capacitor is connected to an output terminal of the current information detection amplifier, and a second terminal of the first capacitor is grounded;

a fifth resistor, wherein a first terminal of the fifth resistor is connected to the first terminal of the first capacitor and the output terminal of the current information detection amplifier; and

a second capacitor, wherein a first terminal of the second capacitor is connected to a second terminal of the fifth resistor, and a second terminal of the second capacitor is grounded.

9 . The multi-phase buck converter of claim 1 , wherein switching frequencies of the M converter branches are the same, and a phase shift of a P th converter branch is

(

P

-

1

)

×

360

M

,

where 1≤p≤m and p is a positive integer.

10 . The multi-phase buck converter of claim 1 , wherein the output inductors in the M converter branches are configured to have same parameters and same parasitic resistances.

11 . A chip, comprising:

a die, on which a multi-phase buck converter is provided,

wherein the multi-phase buck converter comprises:

M converter branches connected in parallel, each of the M converter branches comprising a driving module and a power stage output circuit electrically coupled between the driving module and a voltage output terminal, wherein M is an integer greater than 2; and

a loop error amplifier, configured to compare an output voltage at the voltage output terminal with a reference voltage to generate an output voltage error signal,

wherein the driving module in one of the M converter branches, other than a first converter branch, from a second to an Mth converter branch comprises:

a current information error amplifier, configured to receive, as a first terminal input, a detection voltage across an output inductor of the power stage output circuit in the one of the M converter branches, to receive, as a second terminal input, a detection voltage across an output inductor of the power stage output circuit in a previous converter branch, and to compare the first terminal input with the second terminal input to generate a current information error signal;

a synchronous ramp voltage generation circuit, configured to generate a synchronous ramp signal based on the output voltage at the voltage output terminal;

a pulse width modulation comparator, configured to superimpose the current information error signal to the output voltage error signal to generate a modulation voltage signal, and compare the modulation voltage signal with the synchronous ramp signal to generate a duty cycle modulation set signal; and

a driving control circuit, configured to generate a driving signal based on the duty cycle modulation set signal, such that the power stage output circuit in the one of the M converter branches outputs the output voltage based on the driving signal,

wherein an input terminal of one of the power stage output circuits is electrically coupled to an output terminal of a corresponding driving module through a first trace on the die, an output terminal of the power stage output circuit is electrically coupled to the voltage output terminal through a second trace on the die, and the voltage output terminal is configured to be electrically coupled to a load;

wherein the driving control circuit in the one of the M converter branches comprises:

an RS flip-flop, configured to generate a duty cycle signal based on the duty cycle modulation set signal; and

a switch driving circuit, configured to generate the driving signal based on the duty cycle signal;

wherein the driving module in the one of the M converter branches further comprises:

an adaptive constant-on-time generation circuit, configured to generate a duty cycle reset signal based on the duty cycle signal and a reference switching frequency of the one of the M converter branches,

wherein the RS flip-flop is configured to generate the duty cycle signal based on the duty cycle modulation set signal and the duty cycle reset signal;

wherein the adaptive constant-on-time generation circuit is configured to:

generate a frequency error signal based on the duty cycle signal and the reference switching frequency:

generate an adaptive on-capacitance voltage signal based on the duty cycle signal; and

generate the duty cycle reset signal based on the frequency error signal and the adaptive on-capacitance voltage signal;

wherein the synchronous ramp voltage generation circuit in the one of the M converter branches is configured to:

generate the synchronous ramp signal based on the output voltage and a voltage at a switch output terminal of the power stage output circuit in the one of the M converter branches,

wherein the output inductor is electrically coupled between the switch output terminal and the voltage output terminal.

12 . The chip of claim 11 , wherein the driving module in the first converter branch of the M converter branches comprises:

a synchronous ramp voltage generation circuit, configured to generate a synchronous ramp signal based on the output voltage at the voltage output terminal;

a pulse width modulation comparator, configured to compare the output voltage error signal with the synchronous ramp signal to generate a duty cycle modulation set signal; and

a driving control circuit, configured to generate a driving signal based on the duty cycle modulation set signal, such that the power stage output circuit in the first converter branch of the M converter branches outputs the output voltage based on the driving signal.

13 . The chip of claim 11 , wherein the driving module in the first converter branch of the M converter branches comprises:

a current information error amplifier, configured to receive, as a first terminal input, a detection voltage across an output inductor of the power stage output circuit in the first converter branch of the M converter branches, to receive, as a second terminal input, a detection voltage across an output inductor of the power stage output circuit in the Mth converter branch, and to compare the first terminal input with the second terminal input to generate a current information error signal;

a synchronous ramp voltage generation circuit, configured to generate a synchronous ramp signal based on the output voltage at the voltage output terminal;

a pulse width modulation comparator, configured to superimpose the current information error signal to the output voltage error signal to generate a modulation voltage signal, and compare the modulation voltage signal with the synchronous ramp signal to generate a duty cycle modulation set signal; and

a driving control circuit, configured to generate a driving signal based on the duty cycle modulation set signal, such that the power stage output circuit in the first converter branch of the M converter branches outputs the output voltage based on the driving signal.

14 . The chip of claim 11 , wherein the power stage output circuit in the one of the M converter branches comprises the output inductor and an RC circuit electrically coupled in parallel with the output inductor, and the RC circuit comprises a filter resistor and a filter capacitor which are electrically coupled in series,

wherein the filter resistor and the filter capacitor are configured to filter a voltage across the output inductor to obtain the detection voltage corresponding to a current flowing through the output inductor.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (23)