IP Library Patent Application 18927065
Patent Application
App. No. 18/927,065

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

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Quick Facts
Patent No.
US None
App. No.
18/927,065
Abstract

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Claims (35)

1 - 11 . (canceled)

12 . An apparatus comprising:

a decoder to decode an enqueue command instruction;

execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to:

generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations; and

store the work descriptor to a work queue.

13 . The apparatus of claim 12 further comprising:

an accelerator to read the work descriptor from the work queue and to perform the one or more operations based on the operation field and in accordance with the flag.

14 . The apparatus of claim 13 , wherein the accelerator comprises:

an arbiter to select the work descriptor from the work queue; and

an engine to process the work descriptor responsive to selection by the arbiter, the engine to perform the one or more operations based on the operation field.

15 . The apparatus of claim 14 , wherein the arbiter is to select the work descriptor from the work queue ahead of one or more other work descriptors in accordance with a priority associated with the work descriptor, the work queue, or both.

16 . The apparatus of claim 13 , wherein:

if the flag has a first value, the accelerator is to wait to execute the one or more operations until operations associated with prior work descriptors have completed, and

if the flag has a second value, the accelerator is to execute the one or more operations in parallel with one or more of the operations associated with prior work descriptors.

17 . The apparatus of claim 13 , wherein the accelerator is to produce a result of the one or more operations and to store the result based on the address field.

18 . The apparatus of claim 12 , wherein the address field comprises an address space identifier or a process address space identifier (PASID) to identify a region of memory allocated to store data associated with the work descriptor.

19 . The apparatus of claim 17 , wherein the result comprises a completion record stored at an address indicated by the address field, the completion record to include result data for the one or more operations and a status field indicating status of the one or more operations.

20 . The apparatus of claim 12 , wherein the work queue comprises a location in a system memory or a local memory of a device which is to process the work descriptor.

21 . The apparatus of claim 12 , wherein the work descriptor further comprises a user/supervisor field to indicate whether a request which caused the work descriptor to be generated originated from program code operating at a first privilege level or a second privilege level.

22 . A method comprising:

decoding an enqueue command instruction on a processor;

executing, on the processor, the enqueue command instruction;

generate a work descriptor in response to execution of the enqueue command instruction, the work descriptor generated based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations; and

store the work descriptor to a work queue.

23 . The method of claim 22 further comprising:

reading the work descriptor from the work queue by an accelerator; and

performing the one or more operations based on the operation field and in accordance with the flag.

24 . The method of claim 23 further comprising:

selecting the work descriptor from the work queue by an arbiter of the accelerator; and

processing the work descriptor by an engine of the accelerator to perform the one or more operations based on the operation field.

25 . The method of claim 24 wherein selecting the work descriptor is performed in accordance with a priority associated with the work descriptor, the work queue, or both.

26 . The method of claim 22 further comprising:

waiting to execute the one or more operations until operations associated with prior work descriptors have completed if the flag has a first value; and

executing the one or more operations in parallel with one or more of the operations associated with prior work descriptors if the flag has a second value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2026
From: INTEL CORPORATION
To: INTEL PRODUCTS IP LLC
Reel/Frame 075991/0981 →