IP Library › Granted Patent US 12,645,234
Granted Patent B2
US 12,645,234 · App. 18/929,966 · Granted Jun 2, 2026

Low voltage reference generator using MOS devices

Inventors: Weibiao Zhang (Saratoga, CA); Ke Yun (Cupertino, CA); Bruno W. Garlepp (Sunnyvale, CA)
Assignee: Apple Inc.
G05F1/468G05F1/567G05F1/575G05F3/205G05F3/245G05F3/262
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Quick Facts
Patent No.
US 12,645,234
App. No.
18/929,966
Granted
Jun 2, 2026
Kind
B2
Abstract

Techniques for generating reference voltages and reference currents from a supply voltage are disclosed. A disclosed reference voltage and reference current generator circuit includes a combination of transistor (e.g., MOS) devices and interconnect resistors. The interconnect resistors have temperature coefficients that are selected to negate temperature sensitive effects in the transistor devices due to electron mobility temperature behavior in the transistor devices. The interconnect resistors may be implemented as resistor stacks that include interconnected metal layers separated by electrically insulating layers.

Claims (40)

1 . A reference voltage generator for an integrated circuit device, comprising:

a current generator circuit having one or more transistor devices and a first resistor stack with a first temperature coefficient, wherein the current generator circuit is configured to generate a bias current from a supply voltage provided to the current generator circuit;

a first resistor circuit having a second resistor stack with a second temperature coefficient, the first resistor circuit being configured to generate a first voltage from the bias current;

a second resistor circuit having a third resistor stack with a third temperature coefficient and a fourth resistor stack with a fourth temperature coefficient, the second resistor circuit being configured to generate a current reference from the first voltage; and

a third resistor circuit having a fifth resistor stack with a fifth temperature coefficient, the third resistor circuit being configured to generate a reference voltage from the current reference.

2 . The reference voltage generator of claim 1 , wherein the first temperature coefficient is a positive temperature coefficient with an absolute value of at least about 500 ppm/° C.

3 . The reference voltage generator of claim 1 , wherein the second temperature coefficient is a positive temperature coefficient with an absolute value of at most about 200 ppm/° C.

4 . The reference voltage generator of claim 1 , wherein the third temperature coefficient is a positive temperature coefficient with an absolute value of at least about 500 ppm/° C.

5 . The reference voltage generator of claim 1 , wherein the fourth temperature coefficient is a positive temperature coefficient with an absolute value of at most about 200 ppm/° C.

6 . The reference voltage generator of claim 1 , wherein the fifth temperature coefficient is a positive temperature coefficient with an absolute value of at most about 200 ppm/° C.

7 . The reference voltage generator of claim 1 , wherein the third temperature coefficient is a positive temperature coefficient with an absolute value higher than absolute values of any of the first, second, fourth, or fifth temperature coefficients.

8 . The reference voltage generator of claim 1 , wherein the transistor devices are metal-oxide-semiconductor devices that have electron mobility temperature coefficients.

9 . The reference voltage generator of claim 1 , wherein the fifth temperature coefficient is variable to determine a value of the reference voltage.

10 . The reference voltage generator of claim 1 , wherein the second resistor circuit includes a transistor device and an amplifier circuit.

11 . The reference voltage generator of claim 1 , further comprising at least one transistor coupled to the third resistor circuit, the at least one transistor being configured to generate a reference current output from the current reference and the reference voltage.

12 . The reference voltage generator of claim 1 , wherein at least one of the first, second, third, fourth, or fifth resistor stacks includes:

a plurality of metal layers separated by a plurality of electrically insulating layers, the metal layers being connected by vias through the electrically insulating layers, wherein the metal layers have a plurality of metal traces separated by electrically insulating material, the metal traces being interconnected at end portions of the metal traces.

13 . The reference voltage generator of claim 1 , wherein at least two of the first, second, third, fourth, or fifth resistor stacks are coupled in series between a voltage supply and a voltage ground.

14 . An integrated circuit device, comprising:

a current generator circuit having one or more transistor devices and a first resistor stack with a first temperature coefficient, wherein the current generator circuit is configured to generate a bias current from a supply voltage provided to the current generator circuit; and

an output generator circuit, wherein the output generator circuit includes:

a second resistor stack with a second temperature coefficient;

a third resistor stack with a third temperature coefficient;

a fourth resistor stack with a fourth temperature coefficient; and

a fifth resistor stack with a fifth temperature coefficient;

wherein the output generator circuit is configured to generate:

a first voltage from the bias current;

a current reference from the first voltage; and

a reference voltage from the current reference.

15 . The integrated circuit device of claim 14 , wherein the output generator circuit is configured to generate the current reference and the reference voltage based on resistances of the second, third, fourth, and fifth resistor stacks.

16 . The integrated circuit device of claim 14 , wherein the first temperature coefficient is a positive temperature coefficient with an absolute value of at least about 500 ppm/° C., wherein the second temperature coefficient is a positive temperature coefficient with an absolute value of at most about 200 ppm/° C., wherein the third temperature coefficient is a positive temperature coefficient with an absolute value of at least about 500 ppm/° C., wherein the fourth temperature coefficient is a positive temperature coefficient with an absolute value of at most about 200 ppm/° C., and wherein the fifth temperature coefficient is a positive temperature coefficient with an absolute value of at most about 200 ppm/° C.

17 . The integrated circuit device of claim 14 , wherein the output generator circuit includes at least one transistor configured to generate a reference current output from the current reference and the reference voltage.

18 . The integrated circuit device of claim 14 , wherein at least two of the first, second, third, fourth, or fifth resistor stacks are coupled in series between a voltage supply and a voltage ground.

19 . A method for generating a reference voltage for an integrated circuit device, comprising:

receiving, at a current generator circuit in the integrated circuit device, a supply voltage, wherein the current generator circuit has one or more transistor devices and a first resistor stack with a first temperature coefficient;

generating, at the current generator circuit, a bias current from the supply voltage;

generating, at a first resistor circuit having a second resistor stack with a second temperature coefficient, a first voltage from the bias current;

generating, at a second resistor circuit having a third resistor stack with a third temperature coefficient and a fourth resistor stack with a fourth temperature coefficient, a current reference from the first voltage; and

generating, at a third resistor circuit having a fifth resistor stack with a fifth temperature coefficient, a reference voltage from the current reference.

20 . The method of claim 19 , further comprising generating, by at least one transistor coupled to the third resistor circuit, a reference current output from the current reference and the reference voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2024
From: ZHANG, WEIBIAO; YUN, KE; GARLEPP, BRUNO W.
To: APPLE INC.
Reel/Frame 069055/0756 →
Continuity (2)
Provisional Application 63665737 · Jun 28, 2024
Related Publication 20260003377A1 · Jan 1, 2026
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