Level shifter and display device including same
A display apparatus includes a display panel configured to display an image, a level shifter configured to extract and output data from a data map of a memory and divide a serial output signal output thereto into a parallel output signal to output periodic signals, based on an enable signal, and a shift register configured to output gate signals which are to be applied to the display panel, based on the periodic signals output from the level shifter.
1 . A display apparatus comprising:
a display panel configured to display an image;
a level shifter configured to obtain output data from a data map of a memory, divide an obtained serial output signal into a parallel output signal, and output periodic signals, based on an enable signal; and
a shift register configured to output gate signals which are to be applied to the display panel, based on the periodic signals output from the level shifter,
wherein the level shifter comprises a controller and a selector configured to generate a selection signal for selecting an operation condition of the controller, based on the enable signal and a driving selection signal,
wherein the controller comprises:
a plurality of markers configured to respectively store address values differentiated from one another;
a counter configured to generate a count signal, based on the enable signal; and
a de-multiplexer configured to output an enable control signal for controlling an enable switch so that the enable signal is applied to the counter and a marker control signal for turning on one of marker switches so that an address value included in one of the plurality of markers is applied to an address signal input terminal of the counter, based on the selection signal.
2 . The display apparatus of claim 1 , wherein:
the controller is configured to extract data from the data map of the memory, based on the enable signal; and
the level shifter comprises a bit split circuit configured to divide the serial output signal into the parallel output signal.
3 . The display apparatus of claim 2 , wherein the controller includes a clock generator and an up-counter,
wherein the clock generator is configured to generate a clock which is to be applied to the up-counter, and
wherein the up-counter is configured to generate the count signal which increases based on the clock output from the clock generator.
4 . The display apparatus of claim 3 , wherein the up-counter is further configured to output an overflow signal through an overflow signal output terminal, and when the overflow signal is input through a reset input terminal of the up-counter, the up-counter resets the count signal.
5 . The display apparatus of claim 2 , wherein the level shifter further includes an output circuit, and the bit split circuit includes a shift register and a buffer,
wherein the shift register of the bit split circuit is configured to divide the serial output signal, output from the memory, into the parallel output signals, based on a bit split operation, and
wherein the buffer is configured to transfer an output signal, output from the shift register of the bit split circuit, to the output circuit.
6 . The display apparatus of claim 5 , wherein the output circuit is configured to up-shift and output a level of an output signal output through the buffer.
7 . The display apparatus of claim 1 , wherein the data map comprises data where logic values to be output by channels for each address are sequentially stored.
8 . The display apparatus of claim 1 , wherein the level shifter shifts an address value of the data map whenever the enable signal is applied to be first logic, and whenever the enable signal is applied to be second logic which is opposite to the first logic, the level shifter extracts, as an output signal, data included in the address value of the data map to output the output signal as the periodic signals.
9 . The display apparatus of claim 1 , comprising a timing controller connected to the level shifter, the timing controller configured to output the enable signal and the driving selection signal,
wherein an input or output condition of the level shifter is changed based on bidirectional data communication with the timing controller.
10 . The display apparatus of claim 9 , wherein the controller further includes an interface and a register,
wherein the controller is further to configured to perform bidirectional data communication with the timing controller based on the interface, and
wherein the register is configured to store a current status of the memory included in the level shifter.
11 . The display apparatus of claim 1 , wherein the level shifter is configured to shift an address value of the data map when the enable signal is applied to be first logic, and when the enable signal is applied to be second logic opposite to the first logic, the level shifter is configured to extract, as an output signal, data included in the address value of the data map to output the output signal as the periodic signals, and
the marker control signal is configured to be applied as a pulse type when the enable signal is applied to be the first logic.
12 . A level shifter comprising:
a memory including a data map where logic values to be output by channels for each address are configured to be sequentially stored;
a controller configured to generate a count signal and obtain data from the data map of the memory, based on an enable signal;
a bit split circuit configured to divide a serial output signal output from the memory into a parallel output signal; and
a selector configured to generate a selection signal for selecting an operation condition of the controller, based on the enable signal and a driving selection signal,
wherein the controller comprises:
a plurality of markers configured to respectively store address values differentiated from one another;
a counter configured to generate a count signal, based on the enable signal; and
a de-multiplexer configured to output an enable control signal controlling an enable switch so that the enable signal is applied to the counter and a marker control signal turning on one of marker switches so that an address value included in one of the plurality of markers is applied to an address signal input terminal of the counter, based on the selection signal.
13 . The level shifter of claim 12 , wherein the controller is configured to shift an address value of the data map when the enable signal is applied to be first logic, and when the enable signal is applied to be second logic opposite to the first logic, the controller is configured to extract, as an output signal, data included in the address value of the data map to output the output signal as periodic signals.
14 . The level shifter of claim 12 , wherein the data map comprises data where logic values to be output by channels for each address are sequentially stored.
15 . The level shifter of claim 12 , wherein the level shifter is configured to shift an address value of the data map when the enable signal is applied to be first logic, and when the enable signal is applied to be second logic which is opposite to the first logic, the level shifter is configured to extract, as an output signal, data included in the address value of the data map to output as the periodic signals, and
the marker control signal is configured to be applied as a pulse type when the enable signal is applied to be the first logic.
16 . The level shifter of claim 12 , wherein the controller includes a clock generator and an up-counter,
wherein the clock generator is configured to generate a clock which is to be applied to the up-counter, and
wherein the up-counter is configured to generate the count signal which increases based on the clock output from the clock generator.
17 . The level shifter of claim 16 , wherein the up-counter is further configured to output an overflow signal through an overflow signal output terminal, and when the overflow signal is input through a reset input terminal of the up-counter, the up-counter resets the count signal.
18 . The level shifter of claim 12 , further comprising an output circuit,
wherein the bit split circuit includes a shift register and a buffer, and
wherein the buffer is configured to transfer an output signal, output from the shift register of the bit split circuit, to the output circuit.
19 . The level shifter of claim 18 , wherein the output circuit is configured to up-shift and output a level of an output signal output through the buffer.