Electronic device having a plurality of chiplets
Provided is an electronic device, including a first chiplet including a system bus, a first interconnect module, and a second interconnect module, and a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or second interconnect interface connected to the second interconnect module, in which, in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed.
1 . An electronic device, comprising:
a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module;
a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module; and
the system bus comprises a switch logic comprising a first logic, wherein
in response to determining that a communication failure occurs between the first chiplet and the second chiplet, the switch logic is activated to change at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet, wherein the first logic is activated in response to determining that a disconnection occurs in at least one path of the transfer path coupled to the switch logic, wherein the transfer path comprises a first path through which information is transmitted to the switch logic, a second path through which the information is transmitted from the switch logic to the first interconnect interface, and a third path through which the information is transmitted from the switch logic to the second interconnect interface, and wherein the first logic comprises a logic that:
connects the first path to the third path in response to determining that a disconnection occurs in at least a part of the second path, and
connects the first path to the second path in response to determining that a disconnection occurs in at least a part of the third path.
2 . The electronic device according to claim 1 , wherein the transfer path comprises a path through which the information is transmitted to the first interconnect interface and a path through which the information is transmitted to the second interconnect interface.
3 . The electronic device according to claim 2 , wherein, in response to a disconnection of at least a part of the path through which the information is transmitted to the first interconnect interface or at least a part of the path through which the information is transmitted to the second interconnect interface, or in response to an occurrence of a communication performance degradation equal to or greater than a predetermined threshold, it is determined that the communication failure occurs between the first chiplet and the second chiplet.
4 . The electronic device according to claim 1 , wherein the system bus comprises a data bus used for data transmission and reception.
5 . The electronic device according to claim 4 , wherein
the information comprises a transaction, and
the switch logic is connected to the data bus to change at least a part of a transfer path through which the transaction is transmitted.
6 . The electronic device according to claim 1 , wherein the switch logic further comprises a second logic that is activated in response to determining that a communication performance degradation equal to or greater than a predetermined threshold occurs in at least a part of the second path or at least a part of the third path.
7 . The electronic device according to claim 6 , wherein
the first path comprises a plurality of sub-paths,
the second logic connects each of the plurality of sub-paths to the second path or the third path in response to determining that the communication performance degradation equal to or greater than the predetermined threshold occurs in at least the part of the second path, and
among the plurality of sub-paths, a number of sub-paths connected to the third path is greater than a number of sub-paths connected to the second path.
8 . An electronic device, comprising:
a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module;
a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module; and
the system bus comprises a distributor, wherein
in response to determining a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed, wherein
the transfer path comprises a fourth path through which information is transmitted to the distributor, a fifth path through which the information is transmitted from the distributor to the first interconnect interface, and a sixth path through which the information is transmitted from the distributor to the second interconnect interface, and
the distributor connects the fifth path or the sixth path to the fourth path in response to determining that no communication failure has occurred.
9 . The electronic device according to claim 8 , wherein
the distributor connects the fourth path to the sixth path in response to determining that a communication failure occurs in the fifth path, and
the distributor connects the fourth path to the fifth path in response to determining that a communication failure occurs in the sixth path.
10 . The electronic device according to claim 8 , wherein the information transmitted to the second chiplet through the distributor is a control transaction.
11 . The electronic device according to claim 8 , wherein
the system bus comprises a control bus that transmits a control signal, and
the control signal is transmitted to at least one of the first interconnect module or the second interconnect module.
12 . An electronic device, comprising:
a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module; and
a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module; wherein
in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed, wherein
the information transmitted to the second chiplet using the first interconnect interface is transmitted based on a first clock,
the information transmitted to the second chiplet using the second interconnect interface is transmitted based on a second clock, and
the first clock and the second clock are different from each other.
13 . The electronic device according to claim 12 , wherein
the system bus operates based on a third clock different from the first clock and the second clock, and
the information transmitted to the second chiplet using the first interconnect interface or the second interconnect interface is transmitted to the first interconnect interface or the second interconnect interface through an asynchronous First-In, First-Out (FIFO).
14 . The electronic device according to claim 13 , wherein
the first clock is generated in the first interconnect module, and
the second clock is generated in the second interconnect module.
15 . An electronic device, comprising:
a first chiplet comprising a system bus, a first interconnect module, and a second interconnect module; and
a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or a second interconnect interface connected to the second interconnect module, wherein
in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed, wherein
the first interconnect module and the second interconnect module are configured to communicate with each other based on a first protocol, and
at least one of the first chiplet or the second chiplet comprises a third interconnect module configured to communicate with a host based on a second protocol.
16 . The electronic device according to claim 15 , wherein
the first interconnect module and the second interconnect module are modules that support at least one of Universal Chiplet Interconnect Express (UCie), High-Bandwidth Interconnect (HBI), Bunch of Wires (BoW), or extra-short reach (XSR), and
the third interconnect module is a module that supports Peripheral Component Interconnect Express (PCie).
17 . The electronic device according to claim 15 , wherein the system bus is an Advanced extensible Interface (AXI) type bus.