CHIPLET HAVING SAVE AND FORWARD MODULE

1 . A chiplet, comprising:

an interconnect module for connecting to another chiplet;

a bus interface for connecting to at least one functional module in the chiplet; and

a save and forward module connected to the interconnect module and the bus interface, wherein

the save and forward module comprises:

a slave port that receives a transaction from one of the interconnect module or the bus interface;

a data buffer that temporarily stores at least a portion of the transaction; and

a master port that transmits the transaction stored in the data buffer to the other one of the interconnect module or the bus interface, and the transaction is divided into predetermined units and transmitted.

2 . The chiplet according to claim 1 , wherein, in response to determining that entire transaction is stored in the data buffer, the master port transmits the entire transaction.

3 . The chiplet according to claim 1 , wherein

the transaction is a burst transaction transmitted with a burst transfer method,

the burst transaction comprises a plurality of bits, and

the predetermined unit is a bit unit.

4 . The chiplet according to claim 1 , wherein

the chiplet is a receiver side chiplet that receives the transaction from the other chiplet,

the slave port receives the transaction from the interconnect module, and

the master port transmits the transaction to the bus interface.

5 . The chiplet according to claim 4 , wherein the bus interface is an Advanced extensible Interface (AXI) type interface.

6 . The chiplet according to claim 3 , wherein the save and forward module further comprises:

a transaction decoder that receives the plurality of bits from the slave port; and

a transaction counter that receives information associated with each bit received from the transaction decoder.

7 . The chiplet according to claim 6 , wherein the transaction counter determines whether all of the plurality of bits are received, and in response to determining that all of the plurality of bits are received, causes the master port to transmit all of the plurality of bits stored in the data buffer.

8 . The chiplet according to claim 6 , wherein the transaction decoder determines that the transaction is a burst transaction, based on control information included in a first bit received from the slave port.

9 . The chiplet according to claim 8 , wherein, in response to determining that the transaction is the burst transaction, the transaction decoder stores the bits received from the slave port in the data buffer.

10 . The chiplet according to claim 8 , wherein the transaction counter generates a first error signal based on the control information and a data size of the transaction.

11 . The chiplet according to claim 10 , wherein

the save and forward module further comprises an interrupt handler, and

the interrupt handler receives the first error signal from the transaction counter, generates a first interrupt based on the first error signal, and transmits the first interrupt to a host.

12 . The chiplet according to claim 6 , wherein the save and forward module further comprises a transaction time table register that manages a transaction time table associated with the transaction.

13 . The chiplet according to claim 12 , wherein the transaction time table comprises at least one of a validity of the transaction, an ID of the transaction, a transmission start time, a transmission end time, an error occurrence time, or an error flag.

14 . The chiplet according to claim 12 , wherein

the save and forward module further comprises a timer, and

the transaction time table register records at least one of a transmission start time, a transmission end time, or an error occurrence time of the transaction in the transaction time table using the timer.

15 . The chiplet according to claim 12 , wherein

the save and forward module further comprises a comparator that generates a second error signal associated with a transmission time of the transaction, and

in response to determining that a predetermined error time threshold has been exceeded since a transmission start time of the transaction recorded in a time table of the transaction, the comparator generates the second error signal.

16 . The chiplet according to claim 15 , wherein

the save and forward module further comprises an interrupt handler, and

the interrupt handler receives the second error signal from the comparator, generates a second interrupt based on the second error signal, and transmits the second interrupt to a host.

17 . The chiplet according to claim 16 , wherein, while some of the plurality of bits are stored in the data buffer, access to the slave port by the at least one functional module is allowed.

18 . The chiplet according to claim 1 , wherein

the chiplet is a transmitter side chiplet that transmits the transaction to the other chiplet,

the slave port receives the transaction from the bus interface, and

the master port transmits the transaction to the interconnect module.

19 . The chiplet according to claim 3 , wherein

the slave port transmits to the data buffer whenever the slave port receives a plurality of bits included in the transaction in units of bits,

the data buffer sequentially stores the received bits, and

before all of the plurality of bits are stored in the data buffer, transmission of at least one bit stored in the buffer is not performed.

20 . The chiplet according to claim 1 , wherein a size of the data buffer is determined based on a data size of the transaction.