Adaptive step delay in peripheral trigger generator
A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a “wait for software trigger” command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.
1 . A microcontroller comprising:
a central processing unit (CPU);
a plurality of peripheral units coupled with said CPU; and
a peripheral trigger generator operating independently from the CPU and being coupled with the plurality of peripheral units, wherein the peripheral trigger generator comprises a state machine which is programmable via said CPU by a plurality of sequential programming steps, wherein a variable step delay command is interleaved with at least one output trigger command, wherein the peripheral trigger generator is configured to:
receive a plurality of input signals,
depending on a programming of the state machine, select at least one of said plurality of input signals, and
independent from the CPU, control a function of a selected one of said plurality of peripheral units depending on the selected input signal and the programming of the state machine,
wherein the state machine generates at least one output signal to control the function of the selected peripheral unit.
2 . The microcontroller according to claim 1 , wherein the state machine of the peripheral trigger generator comprises control logic receiving said selected input signal, a programmable step queue controlled by said control logic and comprising a plurality of registers storing said sequential programming steps and a command decoder coupled with the control logic and operable to receive the sequential programming steps and to generate the at least one output signal.
3 . The microcontroller according to claim 1 , wherein the at least one output signal is a trigger signal that controls one of said peripheral units independently from said CPU.
4 . The microcontroller according to claim 3 , wherein said one peripheral unit is an analog-to-digital converter.
5 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that causes the peripheral trigger generator to wait for a variable step delay trigger condition of a selected input signal and to execute a following programming step said selected input signal meets the variable step delay trigger condition.
6 . The microcontroller according to claim 5 , wherein the variable step delay trigger condition is a bit transition from 0 to 1.
7 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that causes the peripheral trigger generator before executing a following programming step to wait for a variable step delay trigger condition.
8 . The microcontroller according to claim 7 , wherein the variable step delay trigger condition is provided by setting a bit by the CPU in a control register of the peripheral trigger generator.
9 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that generates an interrupt signal fed to said CPU.
10 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that jumps to another programming step when a condition is fulfilled.
11 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that generates said at least one output signal.
12 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that broadcasts a plurality of output signals.
13 . The microcontroller according to claim 1 , wherein each programming step of the sequential programming steps comprises a command code and a parameter code.
14 . The microcontroller according to claim 1 , further comprising a watchdog timer wherein the watchdog timer is reset after completion of a programming step and a timeout of the watchdog timer stops execution of the sequential programming steps.
15 . The microcontroller according to claim 14 , wherein a timeout of the watchdog timer is programmable.
16 . The microcontroller according to claim 14 , wherein a timeout of the watchdog timer generates an interrupt fed to the CPU.
17 . The microcontroller according to claim 1 , wherein the peripheral trigger generator is configured to generate a plurality of output signals for a predefined number of peripheral units, wherein each output signal is generated upon execution of a programming step.
18 . The microcontroller according to claim 1 , wherein the peripheral trigger generator is configured to further generate a strobed output signal upon execution of a programming step, wherein the strobed output signal comprises a plurality of parallel output signals.
19 . The microcontroller according to claim 18 , wherein a value of the strobed output signal is provided by a parameter coded within the programming step.
20 . The microcontroller according to claim 19 , wherein the value has n bits and is extended to a bit width being greater than n.
21 . The microcontroller according to claim 19 , wherein the strobed output signal is used to select a channel of an analog to digital converter.