IP Library Granted Patent US 12,579,069
Granted Patent B2
US 12,579,069 · App. 18/948,380 · Granted Mar 17, 2026

Neural processing device

Inventors: Jinseok Kim (Seongnam-si, KR); Jinwook Oh (Seongnam-si, KR); Donghan Kim (Seongnam-si, KR)
Assignee: Rebellions Inc.
G06F12/084G06F2212/622
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Quick Facts
Patent No.
US 12,579,069
App. No.
18/948,380
Granted
Mar 17, 2026
Kind
B2
Abstract

A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.

Claims (34)

1 . A method of operating a neural processing device comprising:

issuing, by an LSU (Load/Store Unit), at least one instruction, the at least one instruction including at least one load instruction of data issued by a neural core load unit or at least one store instruction for transmitting and storing the data issued by a neural core store unit;

providing, by a sync ID logic included in the LSU, at least one sync ID to the neural core load unit or the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID; and

storing, by the sync ID logic, at least one synchronization signal associated with the at least one sync ID in a sync queue.

2 . The method of claim 1 , wherein the at least one instruction comprises at least one group, and

each of the at least one group comprises at least one operation instruction corresponding to either the at least one load instruction or the at least one store instruction and the synchronization signal indicating completion of an issue of the at least one operation instruction.

3 . The method of claim 2 , wherein the storing the at least one synchronization signal comprises:

storing, by a current sync ID register included in the sync ID logic, the at least one sync ID associated with the at least one group of the at least one instruction being issued;

updating, by a sync ID counter included in the sync ID logic, a plurality of counters according to the number of issue of the at least one operation instruction and at least one interconnection return for the at least one instruction for the at least one sync ID; and

storing, by the sync queue included in the sync ID logic, the at least one synchronization signal by a group, and

the method further comprises sending out, by the sync queue, the at least one synchronization signal if an associate counter of the plurality of counters becomes 0.

4 . The method of claim 3 , wherein the at least one group comprises a first group and a second group, and

the sync ID counter comprises:

a first counter configured to count MOs of the first group; and

a second counter configured to count MOs of the second group.

5 . The method of claim 4 , wherein the updating the plurality of counters comprises increasing the first counter by 1 each time an operation instruction of the first group is returned.

6 . The method of claim 4 , wherein the updating the plurality of counters comprises decreasing the first counter by 1 each time an interconnection return for an operation instruction of the first group is returned.

7 . The method of claim 4 , wherein the storing the at least one synchronization signal comprises:

storing a synchronization signal of the first group when issued; and

storing a synchronization signal of the second group in sequence subsequent to the synchronization signal of the first group when issued, and

wherein the sending out the at least one synchronization signal comprises:

outputting the synchronization signal of the first group when the first counter becomes 0; and

outputting the synchronization signal of the second group when the second counter becomes 0.

8 . The method of claim 7 , wherein the synchronization signal of the first group and the synchronization signal of the second group are output in sequence.

9 . The method of claim 4 , wherein the at least one group further comprises a third group,

the first group and the second group have a dependency on each other, and

the third group is independent of the first group and the second group.

10 . The method of claim 9 , wherein a first time between an issue end time of the at least one operation instruction of the first group and an issue start time of the at least one operation instruction of the second group is equal to a second time between an issue end time of the at least one operation instruction of the second group and an issue start time of the at least one operation instruction of the third group.

11 . The method of claim 1 , wherein the sync queue is of a FIFO (First In, First Out) structure.

12 . The method of claim 3 , wherein the storing the at least one sync ID comprises changing and storing the sync ID of a group corresponding to the synchronization signal after a preset fixed cycle if the synchronization signal is issued.

13 . The method of claim 2 , further comprising transmitting, by the LSU, an interconnection request according to the at least one operation instruction to a local interconnection if the at least one operation instruction is issued, and

wherein time points of a transmission of the interconnection request and an issue of the at least one operation instruction differ by a preset fixed cycle.

14 . The method of claim 13 , further comprising receiving, by the LSU, an interconnection return corresponding to the interconnection request from the local interconnection, and

wherein time points of a reception of the interconnection return and the transmission of the interconnection request differ by a non-fixed cycle that is not predetermined.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVING PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 71344 FRAME: 934. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Oct 21, 2025
From: REBELLIONS INC.
To: REBELLIONS INC.
Reel/Frame 073150/0270 →
MERGER AND CHANGE OF NAME Recorded May 21, 2025
From: REBELLIONS INC.; SAPEON KOREA INC.
To: REBELLIONS INC.
Reel/Frame 071344/0934 →
Priority Claims (1)
KR 10-2022-0040666 · Mar 31, 2022 · national
Continuity (3)
Continuation 18448102 · Aug 10, 2023
Continuation 18057183 · Nov 18, 2022
Related Publication 20250077432A1 · Mar 6, 2025
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