Self-Adaptation LDPC Min-Sum Soft Decoder for Different NAND VT Distributions
A method and memory system for decoding data read from a storage of a memory system. The method reads the data stored in the storage of the memory system with read voltages spanning a range of voltage threshold distributions and including voltages within each of the voltage threshold distributions. The method further divides the range into bins spanning the range; generates initial log likelihood ratio values for each bin and generating a bin sequence bn of bin positions; and adjusts values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage.
1 . A method for decoding data read from a storage of a memory system, comprising:
reading the data stored in the storage of the memory system with read voltages spanning a range of voltage threshold distributions and including voltages within each of the voltage threshold distributions;
dividing the range into bins spanning the range;
generating initial log likelihood ratio values for each bin and generating a bin sequence of bin positions; and
adjusting values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage.
2 . The method of claim 1 , wherein the generating initial log likelihood ratio values for each bin comprises generating a channel log likelihood ratio sequence for decoding data read from the storage.
3 . The method of claim 2 , wherein the adjusting the log likelihood ratio values for each bin comprises:
a) conducting low density parity check (LDPC) min-sum decoding with the initial log likelihood ratio values, and thereby generating an intermediate decoded sequence;
b) calculating a checksum on the intermediate decoded sequence;
c) if the checksum of the intermediate decoded sequence is zero, terminating decoding of the data read from the storage;
d) if the checksum of the intermediate decoded sequence is not zero, generating updated log likelihood ratio values based on values in the intermediate decoded sequence; and
e) using the updated log likelihood ratio values as the channel log likelihood ratio sequence for decoding of the data read from the storage.
4 . The method of claim 3 , wherein the generating updated log likelihood ratio values comprises:
calculating log likelihood ratios at a) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (0, j) and b) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (1, j).
5 . The method of claim 4 , wherein the calculating a log likelihood ratio utilizes a bucket counter for counting a) the number of positions in the intermediate decoded sequence and the bin label sequence with the pattern (0, j) and b) the number of positions in the intermediate decoded sequence and the bin label sequence with the pattern (1, j).
6 . The method of claim 1 , further comprising receiving the data to be stored in the storage, scrambling the data, then encoding the data, and thereafter storing the data in the storage.
7 . The method of claim 1 , further comprising receiving the data to be stored in the storage, encoding the data, then scrambling the data, and thereafter storing the data in the storage.
8 . The method of claim 7 , further comprising:
flipping a sign of the initial log likelihood ratio values;
decoding the data with the initial log likelihood ratio values to produce an intermediate decoded sequence, and
scrambling the intermediate decoded sequence prior to the adjusting values of the initial log likelihood ratio values.
9 . The method of claim 1 , wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions.
10 . The method of claim 1 , wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions as the storage is used over time.
11 . A memory system, comprising:
a storage for storing data therein;
an encoder for encoding the data prior to storing the data in the storage;
a decoder for decoding the data after the data is read from the storage; and
a controller for controlling processing of the data read from the storage, the controller configured to:
read the data stored in the storage of the memory system with read voltages spanning a range of voltage threshold distributions and including voltages within each of the voltage threshold distributions;
divide the range into bins spanning the range;
generate initial log likelihood ratio values for each bin and producing a bin sequence of bin positions; and
adjust values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage.
12 . The memory system of claim 11 , wherein the controller is configured to generate a channel log likelihood ratio sequence for decoding data read from the storage.
13 . The memory system of claim 12 , wherein the controller is configured to:
a) conduct low density parity check (LDPC) min-sum decoding with the initial log likelihood ratio values, and thereby generate an intermediate decoded sequence;
b) calculate a checksum on the intermediate decoded sequence d i ;
c) if the checksum of the decoded sequence d i is zero, terminate decoding of the data read from the storage;
d) if the checksum of the intermediate decoded sequence is not zero, generate updated log likelihood ratio values based on values in the intermediate decoded sequence; and
e) use the updated log likelihood ratio values as the channel log likelihood ratio sequence for decoding of the data read from the storage.
14 . The memory system of claim 13 , wherein the controller is configured to:
calculate log likelihood ratios at a) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (0, j) and b) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (1, j).
15 . The memory system of claim 14 , further comprising a bucket counter configured to count a) the number of positions in the intermediate decoded sequence and the bin label sequence with pattern (0, j) and b) the number of positions in the intermediate decoded sequence and the bin label sequence with pattern (1, j).
16 . The memory system of claim 15 , further comprising a scrambler disposed before the encoder, and wherein the controller is configured to:
read the data, scramble the data, then encode the data, and thereafter store the data in the storage.
17 . The memory system of claim 15 , further comprising a scrambler disposed after the encoder, and wherein the controller is configured to:
read the data, encode the data, then scramble the data, and thereafter store the data in the storage.
18 . The memory system of claim 17 , wherein the controller is configured to:
flip a sign of the initial log likelihood ratio values;
decode the data with the initial log likelihood ratio values to produce an intermediate decoded sequence and
scramble an intermediate decoded sequence prior to the adjusting values of the initial log likelihood ratio values.
19 . The memory system of claim 11 , wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions.
20 . The memory system of claim 11 , wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions as the storage is used over time.