Method and System for Channel Estimation and Decoding Acceleration for Irregular LDPC Codes
A method for decoding data read from a memory and associated memory system. The method receives the data read from the memory as a read sequence of bits r i ; decodes the read sequence using an irregular low density parity check (LDPC) matrix to produce a decoded sequence of bits d i ; detects with a deep neural network (DNN) convergence of t bits of the decoded sequence of bits d i from a high degree column zone of the LDPC matrix; and establishes channel log likelihood ratios (LLRs) by modifying initial LLRs to the LLRs estimated by channel estimator using the t decoded bits in the high degree column zone of the LDPC matrix once the convergence is detected by the DNN.
1 . A method for decoding data read from a memory, comprising:
receiving the data read from the memory as a read sequence of bits r i ;
decoding the read sequence using an irregular low density parity check (LDPC) matrix to produce a decoded sequence of bits d i ;
detecting with a deep neural network (DNN) convergence of t bits of the decoded sequence of bits d i from a high degree column zone of the LDPC matrix; and
establishing channel log likelihood ratios (LLRs) by modifying initial LLRs to the LLRs estimated by a channel estimator using the t decoded bits in the high degree column zone of the LDPC matrix once the convergence is detected by the DNN.
2 . The method of claim 1 , further comprising:
after the establishing of the channel LLRs, decoding the bits r i with the established channel LLRs.
3 . The method of claim 1 , wherein the detecting with the DNN of the convergence of the t bits comprises utilizing a pre-trained DNN.
4 . The method of claim 3 , wherein the detecting with the pretrained DNN of the convergence of the t bits comprises inputting to the pretrained DNN a checksum of the decoded sequence of bits d i .
5 . The method of claim 3 , wherein the detecting with the pretrained DNN of the convergence of the t bits comprises inputting to the pretrained DNN a number of bit flips (NoBF) between the read sequence of bits r i and the decoded sequence of bits d i .
6 . The method of claim 1 , wherein the LDPC matrix comprises degree groups including the high degree column zone, a median degree column zone, and a low degree column zone.
7 . The method of claim 1 , wherein the receiving of the data read from the memory comprises hard reading of the data from memory.
8 . The method of claim 7 , wherein the modifying of the initial LLRs comprises:
determining a number of positions B 00 in the sequences d i and r i such that d i =0 and r i =0, i=0, 1, . . . , . . . , t−1;
determining a number of positions B 01 in the sequences d i and r i such that d i =0 and r i =1, i=0, 1, . . . , . . . , t−1;
determining a number of positions B 10 in the sequences d i and r i such that d i =1 and r i =0, i=0, 1, . . . , . . . , t−1;
determining a number of positions B 11 in the sequences d i and r i such that d i =1 and r i =1, i=0, 1, . . . , . . . , t−1; and
calculating for the channel LLRs updated LLRs based on B 00 , B 01 , B 10 , and B 11 .
9 . The method of claim 1 , wherein the receiving of the data read from the memory comprises soft reading of the data from memory.
10 . The method of claim 9 , wherein the modifying of the initial LLRs comprises:
dividing a range of a read voltage threshold distribution for the soft reading of the data from the memory into bins spanning the range;
setting the initial LLRs for each bin;
applying the initial LLRs to the soft read data to generate the decoded sequence of bits d i ;
determining a number of positions B 0k in the sequences d i and s i such that d i =0 and s i =k, i=0, 1, . . . , . . . , t−1;
determining a number of positions B 1k in the sequences d i and s i such that d i =1 and s i =k, i=0, 1, . . . , . . . , t−1; and
calculating for the channel LLRs updated LLRs based on the numbers B 0k and B 1k .
11 . A memory system, comprising:
a storage; and
a decoder coupled to the storage,
wherein the decoder is configured to:
receive the data read from the memory as a read sequence of bits r i ;
decode the read sequence using an irregular low density parity check (LDPC) matrix to produce a decoded sequence of bits d i ;
detect with a deep neural network (DNN) convergence of t bits of the decoded sequence of bits d i from a high degree column zone of the LDPC matrix; and
establish channel log likelihood ratios (LLRs) by modifying initial LLRs to the LLRs estimated by a channel estimator using the t decoded bits in the high degree column zone of the LDPC matrix once the convergence is detected by the DNN.
12 . The memory system of claim 11 , wherein the decoder is configured to, after the establishing of the channel LLRs, decode the bits r i with the established channel LLRs.
13 . The memory system of claim 11 , wherein the decoder is configured to utilize a pre-trained DNN.
14 . The memory system of claim 13 , wherein the decoder is configured to input to the pretrained DNN a checksum of the decoded sequence of bits d i .
15 . The memory system of claim 13 , wherein the decoder is configured to input to the pretrained DNN a number of bit flips (NoBF) between the read sequence of bits r i and the decoded sequence of bits d i .
16 . The memory system of claim 11 , wherein the LDPC matrix comprises degree groups including the high degree column zone, a median degree column zone, and a low degree column zone.
17 . The memory system of claim 14 , wherein the decoder is configured to hard read the data from memory.
18 . The memory system of claim 17 , wherein the decoder is configured to:
determine a number of positions B 00 in the sequences d i and r i such that d i =0 and r i =0, i=0, 1, . . . , . . . , t−1;
determine a number of positions B 01 in the sequences d i and r i such that d i =0 and r i =1, i=0, 1, . . . , . . . , t−1;
determine a number of positions B 10 in the sequences d i and r i such that d i =1 and r i =0, i=0, 1, . . . , . . . , t−1;
determine a number of positions B 11 in the sequences d i and r i such that d i =1 and r i =1, i=0, 1, . . . , . . . , t−1; and
calculate for the channel LLRs updated LLRs based on B 00 , B 01 , B 10 , and B 11 .
19 . The memory system of claim 11 , wherein the decoder is configured to soft read the data from memory.
20 . The memory system of claim 19 , wherein the decoder is configured to:
divide a range of a read voltage threshold distribution for the soft reading of the data from the memory into bins spanning the range;
set the initial LLRs for each bin;
apply the initial LLRs to the soft read data to generate the decoded sequence of bits d i ;
determine a number of positions B 0k in the sequences d i and s i such that d i =0 and s i =k, i=0, 1, . . . , . . . , t−1;
determine a number of positions B 1k in the sequences d i and s i such that d i =1 and s i =k, i=0, 1, . . . , . . . , t−1; and
calculate for the channel LLRs updated LLRs based on the numbers B 0k and B 1k .