VERTICAL INTERCONNECT ELEVATOR BASED ON THROUGH SILICON VIAS

1 . A multi-chip package comprising:

a first integrated-circuit (IC) chip comprising:

a first silicon substrate,

a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers,

a first metal contact on and at a top of the first interconnection scheme and at a top of the first integrated-circuit (IC) chip, wherein the first metal contact comprises a first copper layer at the top of the first integrated-circuit (IC) chip, and

a first polymer layer on the first interconnection scheme, at the top of the first integrated-circuit (IC) chip and in contact with a sidewall of the first metal contact;

a second integrated-circuit (IC) chip at a same first horizontal level as the first integrated-circuit (IC) chip, wherein the second integrated-circuit (IC) chip comprises:

a second silicon substrate,

a second interconnection scheme over the second silicon substrate, wherein the second interconnection scheme comprises a third interconnection metal layer over the second silicon substrate, a fourth interconnection metal layer over the third interconnection metal layer and a second insulating dielectric layer between the third and fourth interconnection metal layers,

a second metal contact on and at a top of the second interconnection scheme and at a top of the second integrated-circuit (IC) chip, wherein the second metal contact comprises a second copper layer at the top of the second integrated-circuit (IC) chip, and

a second polymer layer on the second interconnection scheme, at the top of the second integrated-circuit (IC) chip and in contact with a sidewall of the second metal contact;

a first sealing layer at the same first horizontal level as the first and second integrated-circuit (IC) chips and having a portion horizontally between the first and second integrated-circuit (IC) chips, wherein the first sealing layer has a top surface coplanar with a top surface of each of the first and second polymer layers;

an interconnection bridge over the top surface of each of the first sealing layer and first and second polymer layers and across the portion of the first sealing layer and an edge of each of the first and second integrated-circuit (IC) chips, wherein the interconnection bridge comprises:

a third silicon substrate,

a third interconnection scheme under the third silicon substrate, wherein the third interconnection scheme comprises a fifth interconnection metal layer under the third silicon substrate, a sixth interconnection metal layer under the fifth interconnection metal layer and a third insulating dielectric layer between the fifth and sixth interconnection metal layers,

a first metal bump on and at a bottom of the third interconnection scheme and at a bottom of the interconnection bridge, wherein the first metal bump couples to the first metal contact and comprises a tin-containing cap, and

a second metal bump on and at the bottom of the third interconnection scheme and at the bottom of the interconnection bridge, wherein the second metal bump couples to the second metal contact and comprises a tin-containing cap, wherein the first metal contact of the first integrated-circuit (IC) chip couples to the second metal contact of the second integrated-circuit (IC) chip through the interconnection bridge;

a second sealing layer at a same second horizontal level as the interconnection bridge and over the top surface of each of the first sealing layer and first and second polymer layers, wherein the interconnection bridge is horizontally between a first and a second portion of the second sealing layer, wherein the second sealing layer has a sidewall at a peripheral edge of the second sealing layer and vertically aligned with a sidewall of the first sealing layer at a peripheral edge of the first sealing layer, wherein the sidewall of the first sealing layer is coplanar, in a vertical direction, with the sidewall of the second sealing layer;

a metal interconnect in the vertical direction for vertical interconnection and at the same second horizontal level as the interconnection bridge and second sealing layer;

a fourth interconnection scheme over the interconnection bridge, second sealing layer and metal interconnect, wherein the fourth interconnection scheme comprises:

a fourth insulating dielectric layer over the interconnection bridge and second sealing layer, wherein a first opening in the fourth insulating dielectric layer is vertically over the metal interconnect.

a seventh interconnection metal layer on a top surface of the fourth insulating dielectric layer, extending downwards into the first opening and in contact with the metal interconnect, and

a fifth insulating dielectric layer over the seventh interconnection metal layer and fourth insulating dielectric layer; and

a plurality of third metal bumps on the fourth interconnection scheme and at a top of the multi-chip package, wherein a first one of the plurality of third metal bumps has a horizontal displacement from the metal interconnect and couples to the metal interconnect through the fourth interconnection scheme, wherein each of the plurality of third metal bumps comprises tin.

2 . The multi-chip package of claim 1 , wherein the third interconnection scheme of the interconnection bridge further comprises a sixth insulating dielectric layer under the sixth interconnection metal layer, wherein a second opening in the sixth insulating dielectric layer is under a bottom surface of the sixth interconnection metal layer, wherein the first metal bump extends upwards into the second opening and in contact with the bottom surface of the sixth interconnection metal layer and further extends under and in contact with a bottom surface of the sixth insulating dielectric layer, wherein the first metal bump protrudes downwards from the bottom surface of the sixth insulating dielectric layer.

3 . The multi-chip package of claim 1 , wherein the first metal bump of the interconnection bridge further comprises a third copper layer between the third interconnection scheme and the tin-containing cap of the first metal bump.

4 . The multi-chip package of claim 3 , wherein the first metal bump of the interconnection bridge further comprises an adhesion metal layer between the third interconnection scheme and the third copper layer of the first metal bump.

5 . The multi-chip package of claim 1 , wherein the fifth interconnection metal layer of the third interconnection scheme of the interconnection bridge comprises a third copper layer and a first adhesion metal layer at a top and a sidewall of the third copper layer.

6 . The multi-chip package of claim 5 , wherein the sixth interconnection metal layer of the third interconnection scheme of the interconnection bridge comprises a conductive metal layer and a second adhesion metal layer at a top of the conductive metal layer and not at a sidewall of the conductive metal layer.

7 . The multi-chip package of claim 1 , wherein the first metal contact of the first integrated-circuit (IC) chip is at a same third horizontal as the first polymer layer of the first integrated-circuit (IC) chip, the second metal contact of the second integrated-circuit (IC) chip and the second polymer layer of the second integrated-circuit (IC) chip.

8 . The multi-chip package of claim 1 , wherein the first interconnection scheme of the first integrated-circuit (IC) chip further comprises a sixth insulating dielectric layer on the second interconnection metal layer, wherein the first metal contact is on the sixth insulating dielectric layer, extending downwards into a second opening in the sixth insulating dielectric layer and in contact with the second interconnection metal layer.

9 . The multi-chip package of claim 8 , wherein the first metal contact of the first integrated-circuit (IC) chip further comprises an adhesion metal layer between the first copper layer of the first metal contact and the first interconnection scheme.

10 . The multi-chip package of claim 9 , wherein the adhesion metal layer comprises titanium.

11 . The multi-chip package of claim 8 , wherein the sixth insulating dielectric layer comprises a polymer.

12 . The multi-chip package of claim 1 further comprising:

a sixth insulating dielectric layer over the top surface of each of the first sealing layer and first and second polymer layers, across the portion of the first sealing layer and the edge of said each of the first and second integrated-circuit (IC) chips and under the interconnection bridge and second sealing layer;

a third metal contact between the first integrated-circuit (IC) chip and interconnection bridge, wherein the third metal contact is on the sixth insulating dielectric layer, extending downwards into a second opening in the sixth insulating dielectric layer, wherein the first metal bump of the interconnection bridge is bonded to the third metal contact into a first metal bonding joint coupling to the first metal contact;

a fourth metal contact between the second integrated-circuit (IC) chip and interconnection bridge, wherein the fourth metal contact is on the sixth insulating dielectric layer, extending downwards into a third opening in the sixth insulating dielectric layer, wherein the second metal bump of the interconnection bridge is bonded to the fourth metal contact into a second metal bonding joint coupling to the second metal contact; and

a fifth metal contact vertically under and coupling to the metal interconnect, wherein the fifth metal contact is on the sixth insulating dielectric layer, extending downwards into a fourth opening in the sixth insulating dielectric layer.

13 . The multi-chip package of claim 12 , wherein the third metal contact further comprises a third copper layer and an adhesion metal layer at a bottom of the third copper layer and not at a sidewall of the third copper layer.

14 . The multi-chip package of claim 13 , wherein the adhesion metal layer comprises titanium.

15 . The multi-chip package of claim 12 further comprising an underfill having a first, a second and a third portion, wherein the first portion of the underfill is between the first integrated-circuit (IC) chip and interconnection bridge and in contact with a sidewall of the first metal bonding joint, wherein the second portion of the underfill is between the second integrated-circuit (IC) chip and interconnection bridge and in contact with a sidewall of the second metal bonding joint, and wherein the third portion of the underfill is over the first integrated-circuit (IC) chip and in contact with a sidewall of the interconnection bridge.

16 . The multi-chip package of claim 1 further comprising a fifth interconnection scheme on the top surface of the first polymer layer of the first integrated-circuit (IC) chip, the top surface of the second polymer layer of the second integrated-circuit (IC) chip and the top surface of the first sealing layer and under the interconnection bridge and second sealing layer, wherein the fifth interconnection scheme comprises:

a sixth insulating dielectric layer on the top surface of the first polymer layer of the first integrated-circuit (IC) chip, the top surface of the second polymer layer of the second integrated-circuit (IC) chip and the top surface of the first sealing layer;

an eighth interconnection metal layer on a top surface of the sixth insulating dielectric layer, wherein the eighth interconnection metal layer extends downwards into a second opening in the sixth insulating dielectric layer and in contact with the first metal contact of the first integrated-circuit (IC) chip and extends downwards into a third opening in the sixth insulating dielectric layer and in contact with the second metal contact of the second integrated-circuit (IC) chip; and

a seventh insulating dielectric layer over the eighth interconnection metal layer and sixth insulating dielectric layer, wherein the eighth interconnection metal layer couples to the first metal bump of the interconnection bridge through a fourth opening in the seventh insulating dielectric layer, couples to the second metal bump of the interconnection bridge through a fifth opening in the seventh insulating dielectric layer and couples to the metal interconnect through a sixth opening in the seventh insulating dielectric layer.

17 . The multi-chip package of claim 1 , wherein the seventh interconnection metal layer of the fourth interconnection scheme comprises a third copper layer and an adhesion metal layer at a bottom of the third copper layer and not at a sidewall of the third copper layer.

18 . The multi-chip package of claim 17 , wherein the third copper layer comprises electroplated copper.

19 . The multi-chip package of claim 1 , wherein the interconnection bridge further comprises a decoupling capacitor having a portion in the third silicon substrate.

20 . The multi-chip package of claim 19 , wherein the interconnection bridge further comprises a through silicon via (TSV) vertically in the third silicon substrate and coupling to the decoupling capacitor through the third interconnection scheme of the interconnection bridge.

21 . The multi-chip package of claim 20 , wherein the decoupling capacitor comprises a metal electrode coupling to the through silicon via (TSV) and a voltage (Vss) of ground reference.

22 . The multi-chip package of claim 1 , wherein the interconnection bridge further comprises a through silicon via (TSV) vertically in the third silicon substrate, wherein a second opening in the fourth insulating dielectric layer of the fourth interconnection scheme is vertically over the through silicon via (TSV), wherein the seventh interconnection metal layer of the fourth interconnection scheme extends downwards into the second opening and in contact with the through silicon via (TSV), wherein a second one of the plurality of third metal bumps couples to the through silicon via (TSV) through the fourth interconnection scheme.

23 . The multi-chip package of claim 1 , wherein the metal interconnect comprises a third copper layer.

24 . The multi-chip package of claim 1 , wherein each of the first and second sealing layers comprises a molding compound.

25 . The multi-chip package of claim 1 , wherein the second sealing layer has a top surface coplanar with a top surface of the interconnection bridge.

26 . The multi-chip package of claim 1 , wherein the first integrated-circuit (IC) chip has a bottom surface coplanar with a bottom surface of multi-and the second integrated-circuit (IC) chip.

27 . The multi-chip package of claim 1 , wherein the first integrated-circuit (IC) chip is a graphic-processing-unit (GPU) integrated-circuit (IC) chip.

28 . The multi-chip package of claim 1 , wherein the first integrated-circuit (IC) chip is a central-processing-unit (CPU) integrated-circuit (IC) chip.

29 . The multi-chip package of claim 1 , wherein the first integrated-circuit (IC) chip is a logic integrated-circuit (IC) chip.

30 . The multi-chip package of claim 1 , wherein each of the first and second integrated-circuit (IC) chips is a graphic-processing-unit (GPU) integrated-circuit (IC) chip.

31 . The multi-chip package of claim 19 , wherein the decoupling capacitor comprises a first and a second metal electrode each having a portion extending vertically in the third silicon substrate and further comprises a dielectric layer having a portion between the portion of the first metal electrode and the portion of the second metal electrode and making contact with both.

32 . The multi-chip package of claim 31 , wherein the dielectric layer of the decoupling capacitor is between a first vertical sidewall of the portion of the first metal electrode and a second vertical sidewall of the portion of the second metal electrode and in contact with the first and second vertical sidewalls.

33 . The multi-chip package of claim 31 , wherein the third interconnection scheme of the interconnection bridge couples to each the first and second metal electrodes of the decoupling capacitor and the first integrated-circuit (IC) chip.

34 . The multi-chip package of claim 31 , wherein the third interconnection scheme of the interconnection bridge couples to the second metal electrode of the decoupling capacitor and each of the first and second integrated-circuit (IC) chips.

35 . The multi-chip package of claim 31 , wherein the first metal electrode comprises a material containing titanium.

36 . The multi-chip package of claim 31 , wherein the dielectric layer of the decoupling capacitor comprises an oxide material.

37 . The multi-chip package of claim 1 , wherein the seventh interconnection metal layer has a top area extending from a first upper space over a left sidewall of the first opening to a second upper space over a right sidewall of the first opening, wherein the top area has a point at a middle between the first and second upper spaces, vertically over the first opening and over a third horizontal level defined by the top surface of the fourth insulating dielectric layer.

38 . The multi-chip package of claim 16 , wherein the eighth interconnection metal layer has a top area extending from a first upper space over a left sidewall of the second opening to a second upper space over a right sidewall of the second opening, wherein the top area has a point at a middle between the first and second upper spaces, vertically over the second opening and over a third horizontal level defined by the top surface of the sixth insulating dielectric layer.