ADC offset correction with partial unscrambled data
Methods and systems are provided for training an analog-to-digital converter (ADC) of a receiver. The methods and systems access a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions and destabilize a clock data recovery (CDR) component to generate a random frequency offset. The methods and systems instruct an ADC to sample the training sequence, using a set of clock signals generated by the phase interpolator (PI) using the CDR component based on the random frequency offset, to generate a set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions. The methods and systems calibrate an ADC offset based on the training sequence that has been sampled by the ADC using the set of clock signals generated by the PI using the CDR component based on the random frequency offset.
1 . A Peripheral Component Interconnect Express (PCIE) receiver comprising:
an analog-to-digital converter (ADC);
a clock data recovery (CDR) component coupled to the ADC via a phase interpolator (PI); and
one or more processors configured to perform operations comprising:
accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;
destabilizing the CDR component to generate a random frequency offset;
instructing the ADC to sample the training sequence, using a set of clock signals generated by the PI using the CDR component based on the random frequency offset, to generate a set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions; and
calibrating an ADC offset based on the training sequence that has been sampled by the ADC using the set of clock signals generated by the PI using the CDR component based on the random frequency offset.
2 . The PCIE receiver of claim 1 , wherein the training sequence is an analog training sequence processed by the ADC, and wherein the plurality of unscrambled portions is interleaved equally with the plurality of scrambled portions.
3 . The PCIE receiver of claim 1 , wherein the CDR component is periodically destabilized.
4 . The PCIE receiver of claim 1 , further comprising:
a low pass filter (LPF) coupled to the CDR component, the CDR component comprising offset correction circuitry for computing the ADC offset; and
a digital-to-analog converter (DAC) coupled to an output of the offset correction circuitry, wherein an output of the ADC is coupled to the LPF, and an output of the PI being coupled to one or more clock dividers configured to generate the set of clock signals.
5 . The PCIE receiver of claim 4 , wherein the CDR component comprises:
an integral path; and
a proportional path, the integral path and the proportional path being coupled to receive a phase error from the LPF, outputs of the integral path and the proportional path being combined and integrated to provide a signal to the PI, and the integral path applying an integral path constant to the phase error and the proportional path applying a proportional path constant to the phase error.
6 . The PCIE receiver of claim 5 , wherein the operations further comprise:
overriding an output of the integral path during calibration of the ADC offset to randomize effect of the plurality of scrambled portions; and
temporarily disabling the proportional path during the calibration of the ADC offset.
7 . The PCIE receiver of claim 6 , wherein the CDR component further comprises:
a multiplexor coupled to receive a first signal generated by applying the integral path constant to the phase error and a second signal comprising a training signal, an output of the multiplexor is coupled via an integrator to a component that combines the outputs of the integral path and the proportional path, wherein the operations further comprise:
providing a select signal to the multiplexor to output the second signal during the calibration of the ADC offset while the ADC samples the training sequence and to output the first signal while the ADC samples a data signal.
8 . The PCIE receiver of claim 7 , wherein the training signal comprises a constant value.
9 . The PCIE receiver of claim 7 , wherein the training signal comprises a random frequency signal generated using a linear feedback shift register (LFSR).
10 . The PCIE receiver of claim 9 , wherein the LFSR generates a random code between two values, and wherein the operations further comprise accessing a map to select a frequency offset to generate the random frequency signal based on the random code.
11 . The PCIE receiver of claim 5 , wherein the operations further comprise:
causing the proportional path to have a proportional gain that is smaller than an integral gain provided by the integral path by a specified amount during calibration of the ADC offset; and
causing the integral path to have the integral gain that is smaller than the proportional gain provided by the proportional path when the ADC samples a data signal after calibration is completed.
12 . The PCIE receiver of claim 11 , wherein the CDR component further comprises:
a first multiplexor having first and second inputs coupled respectively to a first proportional path constant and a second proportional path constant, and a first output of the first multiplexor comprising the proportional path constant coupled to a first component that combines the first output with the phase error; and
a second multiplexor having first and second inputs coupled respectively to a first integral path constant and a second integral path constant, and a second output of the second multiplexor comprising the integral path constant coupled to a second component that combines the second output with the phase error, wherein the first integral path constant is smaller than the first proportional path constant, and wherein the second integral path constant is larger than the second proportional path constant.
13 . The PCIE receiver of claim 12 , wherein the operations further comprise:
generating an unlock signal that is coupled to select inputs of the first and second multiplexors to destabilize the CDR component, the unlock signal when asserted causes the second input, comprising the second proportional path constant, of the first multiplexor to be coupled to the first output of the first multiplexor and causes the second input, comprising the second integral path constant, of the second multiplexor to be coupled to the second output of the second multiplexor.
14 . The PCIE receiver of claim 13 , wherein the unlock signal when de-asserted causes the first input, comprising the first proportional path constant, of the first multiplexor to be coupled to the first output of the first multiplexor and causes the first input, comprising the first integral path constant, of the second multiplexor to be coupled to the second output of the second multiplexor.
15 . The PCIE receiver of claim 12 , wherein an output of the second component is coupled via an integrator to a component that combines the outputs of the integral path and the proportional path.
16 . The PCIE receiver of claim 1 , wherein the operations further comprise randomizing a sampling clock of the ADC to destabilize the CDR component.
17 . The PCIE receiver of claim 1 , wherein the plurality of unscrambled portions of the training sequence comprises four unit intervals (UIs) and the plurality of unscrambled portions in the set of digital symbols comprises four UI.
18 . A method comprising:
accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;
destabilizing a clock data recovery (CDR) component to generate a random frequency offset:
instructing an analog-to-digital converter (ADC) to sample the training sequence, using a set of clock signals generated by a phase interpolator (PI) using the CDR component based on the random frequency offset, to generate a set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions; and
calibrating an ADC offset based on the training sequence that has been sampled by the ADC using the set of clock signals generated by the PI using the CDR component based on the random frequency offset.
19 . The method of claim 18 , wherein the training sequence is an analog training sequence processed by the ADC, and wherein the plurality of unscrambled portions is interleaved equally with the plurality of scrambled portions.
20 . A non-transitory computer-readable medium comprising computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;
destabilizing a clock data recovery (CDR) component to generate a random frequency offset;
instructing an analog-to-digital converter (ADC) to sample the training sequence, using a set of clock signals generated by a phase interpolator (PI) using the CDR component based on the random frequency offset, to generate a set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions; and
calibrating an ADC offset based on the training sequence that has been sampled by the ADC using the set of clock signals generated by the PI using the CDR component based on the random frequency offset.