IP Library › Granted Patent US 12,651,557
Granted Patent B2
US 12,651,557 · App. 18/959,700 · Granted Jun 9, 2026

Display panel and display apparatus

Inventors: Mengmeng Xie (Xiamen, CN); Tianyi Wu (Xiamen, CN); Wenxin Jiang (Xiamen, CN)
Assignee: Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd.
G09G3/32G09G2300/0426G09G2300/0842G09G2300/0861G09G2310/0286G09G2320/0223G09G2320/0233
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Quick Facts
Patent No.
US 12,651,557
App. No.
18/959,700
Granted
Jun 9, 2026
Kind
B2
Abstract

The present application discloses a display panel and a display apparatus. The display panel includes: a light-emitting element; and a pixel circuit and a driving circuit, the driving circuit providing a control signal for the pixel circuit, and the pixel circuit being electrically connected to the light-emitting element; wherein the display panel comprises a first area and a second area, the pixel circuit comprises a first pixel circuit located in the first area and a second pixel circuit located in the second area, a length of the first pixel circuit in a first direction being less than a length of the second pixel circuit in the first direction; the driving circuit comprises a first driving circuit, the first driving circuit comprising a plurality of first shift registers cascaded along a second direction, the first direction intersecting with the second direction.

Claims (120)

1 . A display panel, comprising:

a light-emitting element; and

a pixel circuit and a driving circuit, the driving circuit providing a control signal for the pixel circuit, and the pixel circuit being electrically connected to the light-emitting element,

wherein the display panel comprises a first area and a second area, the pixel circuit comprises a first pixel circuit located in the first area and a second pixel circuit located in the second area, a length of the first pixel circuit in a first direction being less than a length of the second pixel circuit in the first direction, or a distance between adjacent two of the first pixel circuits in the first direction being less than a distance between adjacent two of the second pixel circuits in the first direction;

wherein the driving circuit comprises a first driving circuit, the first driving circuit comprising a plurality of first shift registers cascaded along a second direction, the first direction intersecting with the second direction;

wherein in the second direction, the first shift register and the light-emitting element at least partially overlap;

wherein the pixel circuit comprises a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, a first electrode of the driving transistor is connected to a first power supply terminal through the first light-emitting control transistor, and a second electrode of the driving transistor is connected to the light-emitting element through the second light-emitting control transistor; and

wherein in the first pixel circuit, a distance between the first light-emitting control transistor and the driving transistor in the second direction is D 11 , and a distance between the second light-emitting control transistor and the driving transistor in the second direction is D 12 ,

in the second pixel circuit, a distance between the first light-emitting control transistor and the driving transistor in the second direction is D 21 , and a distance between the second light-emitting control transistor and the driving transistor in the second direction is D 22 ,

wherein D 11 <D 12 , or D 21 =D 22 .

2 . The display panel according to claim 1 , wherein the driving transistor comprises at least a first sub-transistor and a second sub-transistor, a gate of the first sub-transistor is connected to a gate of the second sub-transistor, a first electrode of the first sub-transistor is connected to a first electrode of the second sub-transistor, and a second electrode of the first sub-transistor is connected to a second electrode of the second sub-transistor.

3 . The display panel according to claim 2 , wherein

in the first pixel circuit, the first sub-transistor and the second sub-transistor are arranged along the second direction;

in the second pixel circuit, the first sub-transistor and the second sub-transistor are arranged along the first direction.

4 . The display panel according to claim 2 ,

wherein

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5 . The display panel according to claim 2 , wherein

the pixel circuit further comprises a first reset transistor, a gate of the first reset transistor is connected to a first scanning signal line, a first electrode of the first reset transistor is connected to a reset signal line, and a second electrode of the first reset transistor is connected to a gate of the driving transistor;

the reset signal line is located on a side of the first scanning signal line away from the driving transistor.

6 . The display panel according to claim 5 , wherein

the first electrode of the first reset transistor and the reset signal line are both connected to a first connection portion; the first connection portion and the first scanning signal line partially overlap.

7 . The display panel according to claim 2 , wherein

the pixel circuit further comprises a data writing transistor and a threshold compensation transistor, a first electrode of the data writing transistor is connected to a first electrode of the driving transistor, and a second electrode of the data writing transistor is connected to a data line;

a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, and a second electrode of the threshold compensation transistor is connected to a second electrode of the driving transistor;

in the first pixel circuit, a distance between the data writing transistor and the threshold compensation transistor in the first direction is D 1 ;

in the second pixel circuit, a distance between the data writing transistor and the threshold compensation transistor in the first direction is D 2 , wherein

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D

2.

8 . The display panel according to claim 2 , wherein

the pixel circuit further comprises a first reset transistor and a second reset transistor, the first reset transistor is connected to a gate of the driving transistor, and is configured to provide a first reset signal to the gate of the driving transistor, and the second reset transistor is connected to a first electrode of the light-emitting element, and is configured to provide a second reset signal to the first electrode of the light-emitting element;

in the first pixel circuit, a gate of the first reset transistor is connected to a first scanning signal line, and a gate of the second reset transistor is connected to a second scanning signal line;

in the second pixel circuit, a gate of the first reset transistor is connected to the first scanning signal line, and a gate of the second reset transistor is connected to the first scanning signal line.

9 . The display panel according to claim 8 , wherein

the second scanning signal line connected to the first pixel circuit at an i-th row is reused as the first scanning signal line of the first pixel circuit at an i+1-th row, and i is a positive integer.

10 . The display panel according to claim 9 , wherein

in the first pixel circuit, a distance between the first reset transistor and the driving transistor in the second direction is D 31 , and a distance between the second reset transistor and the driving transistor in the second direction is D 32 ;

in the second pixel circuit, a distance between the first reset transistor and the driving transistor in the second direction is D 41 , and a distance between the second reset transistor and the driving transistor in the second direction is D 42 ; wherein

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11 . The display panel according to claim 8 , wherein

in the first pixel circuit, a distance between the second reset transistor and the driving transistor in the second direction is D 32 ;

in the second pixel circuit, a distance between the second reset transistor and the driving transistor in the second direction is D 42 ;

wherein D 32 >D 42 .

12 . The display panel according to claim 8 , wherein

the pixel circuit further comprises a second light-emitting control transistor, and a second electrode of the driving transistor is connected to the light-emitting element through the second light-emitting control transistor;

in the first pixel circuit, a second electrode of the second reset transistor is connected to a second electrode of the second light-emitting control transistor through a second connection portion;

in the second pixel circuit, a second electrode of the second reset transistor is connected to a second electrode of the second light-emitting control transistor through a third connection portion;

a length of the second connection portion in the second direction is greater than a length of the third connection portion in the second direction.

13 . The display panel according to claim 8 , wherein in the second pixel circuit, a first electrode of the first reset transistor is connected to a first electrode of the second reset transistor through a fourth connection portion; and

the fourth connection portion is connected to a reset signal line through a first connection portion.

14 . The display panel according to claim 1 , wherein a length of the first shift register in the second direction is greater than a length of the first shift register in the first direction.

15 . The display panel according to claim 14 , wherein the first shift register comprises a first output module, the first output module comprises a first output transistor and a second output transistor; wherein

a channel length direction of the first output transistor is parallel to the first direction, and a channel width direction of the first output transistor is parallel to the second direction; or,

a channel length direction of the second output transistor is parallel to the first direction, and a channel width direction of the second output transistor is parallel to the second direction.

16 . The display panel according to claim 15 , wherein the first shift register further comprises a first switch module, and along the second direction, the first switch module is located between the first output transistor and the second output transistor.

17 . The display panel according to claim 14 , wherein the first driving circuit provides a light-emitting control signal for a light-emitting control transistor of the pixel circuit.

18 . The display panel according to claim 1 , wherein the display panel comprises a first pixel column, a second pixel column and a first circuit column sequentially arranged along the first direction;

the first pixel column comprises pixels arranged along the second direction, the second pixel column comprises pixels arranged along the second direction, and the first circuit column comprises a pixel circuit group arranged along the second direction;

the display panel further comprises a first anode connection line, the first anode connection line connects the pixels in the first pixel column to the pixel circuits in the pixel circuit group of the first circuit column;

the first anode connection line overlaps the second pixel column.

19 . A display apparatus, comprising a display panel comprising:

a light-emitting element; and

a pixel circuit and a driving circuit, the driving circuit providing a control signal for the pixel circuit, and the pixel circuit being electrically connected to the light-emitting element,

wherein the display panel comprises a first area and a second area, the pixel circuit comprises a first pixel circuit located in the first area and a second pixel circuit located in the second area, a length of the first pixel circuit in a first direction being less than a length of the second pixel circuit in the first direction, or a distance between adjacent two of the first pixel circuits in the first direction being less than a distance between adjacent two of the second pixel circuits in the first direction;

wherein the driving circuit comprises a first driving circuit, the first driving circuit comprising a plurality of first shift registers cascaded along a second direction, the first direction intersecting with the second direction;

wherein in the second direction, the first shift register and the light-emitting element at least partially overlap;

wherein the pixel circuit comprises a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, a first electrode of the driving transistor is connected to a first power supply terminal through the first light-emitting control transistor, and a second electrode of the driving transistor is connected to the light-emitting element through the second light-emitting control transistor; and

wherein in the first pixel circuit, a distance between the first light-emitting control transistor and the driving transistor in the second direction is D 11 , and a distance between the second light-emitting control transistor and the driving transistor in the second direction is D 12 ,

in the second pixel circuit, a distance between the first light-emitting control transistor and the driving transistor in the second direction is D 21 , and a distance between the second light-emitting control transistor and the driving transistor in the second direction is D 22 ,

wherein D 11 <D 12 , or D 21 =D 22 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2024
From: XIE, MENGMENG; WU, TIANYI; JIANG, WENXIN
To: TIANMA ADVANCED DISPLAY TECHNOLOGY INSTITUTE (XIAMEN) CO.,LTD.
Reel/Frame 069403/0749 →
Priority Claims (1)
CN 202411127690.7 · Aug 16, 2024 · national
Continuity (1)
Related Publication 20260051281A1 · Feb 19, 2026
References Cited (10)
US 11361713B1 · Fu · 2022 [cited by applicant]
US 20220028317A1 · Kim et al. · 2022 [cited by applicant]
US 20230222969A1 · Peng · 2023 [cited by examiner]
US 20240347010A1 · Zhang · 2024 [cited by examiner]
CN 113471225A · 2021 [cited by applicant]
CN 114005411A · 2022 [cited by applicant]
CN 117153106A · 2023 [cited by applicant]
CN 117352530A · 2024 [cited by applicant]
The First Office Action dated Sep. 3, 2025 for Chinese Application No. 202411127690.7 , 22 pages. [cited by applicant]
The extended European search report dated Jan. 2, 2026 for European Application No. 25196061.3 , 20 pages. [cited by applicant]