Pipelined analog-to-digital converter (ADC) and residual voltage generation circuit and generation method thereof
A pipelined analog-to-digital converter (ADC) and a residual voltage generation circuit and generation method thereof are provided. A common mode voltage ADC is configured to convert a common mode voltage of an input signal into a first digital signal; a digital signal processing module is configured to receive the first digital signal and a second digital signal obtained by rough conversion of the input signal by an ADC and output a third digital signal and a fourth digital signal based on the first digital signal and the second digital signal, respectively; a sub-digital-to-analog converter (DAC) is configured to receive the input signals and a switching control signal and output a residual voltage; and based on the third digital signal and the fourth digital signal, a common mode voltage of the residual voltage is approximately equal to a set threshold voltage.
1 . A residual voltage generation circuit, applied to a pipelined analog-to-digital converter (ADC), comprising:
a common mode voltage ADC, configured to receive an input signal and convert a common mode voltage of the input signal into a first digital signal;
an ADC, configured to receive the input signal and convert the input signal into a second digital signal;
a digital signal processing module, configured to receive the first digital signal and the second digital signal and output a third digital signal and a fourth digital signal; and
a sub-digital-to-analog converter (DAC), configured to receive the input signal and a switching control signal and output a residual voltage, wherein the switching control signal is generated based on the third digital signal and the fourth digital signal;
wherein based on the third digital signal and the fourth digital signal, a common mode voltage of the residual voltage generated by the sub-DAC is approximately equal to a set threshold voltage.
2 . The residual voltage generation circuit according to claim 1 , wherein
when a number of bits of the first digital signal is equal to a number of bits of the second digital signal, the third digital signal is equal to a difference by subtracting a binary value corresponding to 2{circumflex over ( )}(N1-1) from a sum of the first digital signal and the second digital signal; the fourth digital signal is equal to a difference by subtracting the second digital signal from a sum of a binary value corresponding to (2{circumflex over ( )}(N1-1)−1) and the first digital signal; and N1 denotes the number of bits of the second digital signal; and
when the number of bits of the first digital signal is not equal to the number of bits of the second digital signal, the digital signal processing module comprises a number-of-bits conversion module for converting the number of bits of the first digital signal to be equal to the number of bits of the second digital signal; wherein the third digital signal is equal to a difference by subtracting the binary value corresponding to 2{circumflex over ( )}(N1-1) from a sum of the first digital signal converted to hold N1 bits and the second digital signal; and the fourth digital signal is equal to a difference by subtracting the second digital signal from a sum of the binary value corresponding to (2{circumflex over ( )}(N1-1)−1) and the first digital signal converted to hold N1 bits.
3 . The residual voltage generation circuit according to claim 2 , wherein a difference between the third digital signal and the fourth digital signal is defined as a first difference;
the digital signal processing module is configured to limit decimal values corresponding to the third digital signal and the fourth digital signal to a range of 0 to (2{circumflex over ( )}N1-1);
when the decimal value corresponding to the third digital signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the decimal value corresponding to the third digital signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged; and
when the decimal value corresponding to the fourth digital signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the decimal value corresponding to the fourth digital signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged.
4 . The residual voltage generation circuit according to claim 3 , wherein
the residual voltage generation circuit further comprises an encoder; and the encoder is configured to receive the third digital signal and the fourth digital signal and output a first switching control signal and a second switching control signal; and
the sub-DAC is configured to generate the residual voltage based on the input signal, the first switching control signal, and the second switching control signal.
5 . The residual voltage generation circuit according to claim 2 , wherein
the residual voltage generation circuit further comprises an encoder; and the encoder is configured to receive the third digital signal and the fourth digital signal and output a first switching control signal and a second switching control signal; and
the sub-DAC is configured to generate the residual voltage based on the input signal, the first switching control signal, and the second switching control signal.
6 . The residual voltage generation circuit according to claim 1 , wherein the digital signal processing module comprises a first digital conversion module, a codeword transfer module, and a second digital conversion module;
the first digital conversion module is configured to output a first conversion signal based on the first digital signal and output a second conversion signal based on the second digital signal;
the codeword transfer module is configured to output a third conversion signal and a fourth conversion signal based on the first conversion signal and the second conversion signal, and make a sum of the third conversion signal and the fourth conversion signal approximately twice the first conversion signal and a decimal difference between the third conversion signal and the fourth conversion signal equal to a difference between a double of a decimal value of the second conversion signal and (2{circumflex over ( )}N1-1); and N1 denotes a number of bits of the second digital signal; and
the second digital conversion module is configured to output the third digital signal based on the third conversion signal and output the fourth digital signal based on the fourth conversion signal.
7 . The residual voltage generation circuit according to claim 6 , wherein
when the first to fourth conversion signals are decimal signals,
the third conversion signal is equal to a difference by subtracting (2{circumflex over ( )}N1-1) from a sum of the second conversion signal and the first conversion signal; and
the fourth conversion signal is equal to a difference by subtracting the second conversion signal from a sum of (2{circumflex over ( )}(N1-1)−1) and the first conversion signal.
8 . The residual voltage generation circuit according to claim 7 , wherein
a difference between the third conversion signal and the fourth conversion signal is defined as a first difference;
the codeword transfer module is configured to limit the third conversion signal and the fourth conversion signal to a range of 0 to (2{circumflex over ( )}N1-1);
when the third conversion signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the third conversion signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged; and
when the fourth conversion signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the fourth conversion signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged.
9 . The residual voltage generation circuit according to claim 1 , wherein
the set threshold voltage is half of a reference voltage.
10 . The residual voltage generation circuit according to claim 1 , wherein
the residual voltage generation circuit further comprises an encoder; and the encoder is configured to receive the third digital signal and the fourth digital signal and output a first switching control signal and a second switching control signal; and
the sub-DAC is configured to generate the residual voltage based on the input signal, the first switching control signal, and the second switching control signal.
11 . The residual voltage generation circuit according to claim 10 , wherein
the sub-DAC comprises a first capacitor array and a second capacitor array; a first terminal of the first capacitor array is connected to a common mode signal through a first switch; and in the first capacitor array, a second terminal of a capacitor is connected to one of a positive terminal of the input signal, a positive terminal of the reference voltage, and a negative terminal of the reference voltage through a first switch array;
a first terminal of the second capacitor array is connected to the common mode signal through a second switch; and in the second capacitor array, a second terminal of a capacitor is connected to one of a negative terminal of the input signal, the positive terminal of the reference voltage, and the negative terminal of the reference voltage through a second switch array;
in a sampling phase, the first switch and the second switch are closed, a second terminal of the first capacitor array is connected to the positive terminal of the input signal, and a second terminal of the second capacitor array is connected to the negative terminal of the input signal; and
in a residual voltage generation phase, the first switch and the second switch are opened, the first switch array is controlled by the first switching control signal, and the second switch array is controlled by the second switching control signal.
12 . A pipelined ADC, comprising cascaded structures of K stages, K being a positive integer greater than 1, wherein a cascaded structure other than a Kth stage comprises the residual voltage generation circuit according to claim 1 ;
an ith-stage cascaded circuit is configured to output an ith amplified signal based on the residual voltage generated by the sub-DAC in the ith-stage cascaded circuit, i being a positive integer greater than or equal to 1 and less than K;
an input signal in a first-stage cascade circuit is an analog signal to be converted; and input signals in cascaded circuits of second to Kth stages each are an amplified signal generated by a previous-stage cascaded circuit;
the input signal in the ith-stage cascaded circuit is the input signal of the residual voltage generation circuit in the ith-stage cascaded circuit; and
based on the second digital signals output by the ADCs in the cascaded structures of first to (K−1)th stages and a fifth digital signal output by the ADC in the Kth-stage cascaded circuit, the pipelined ADC outputs a sixth digital signal through redundant correction.
13 . The pipelined ADC according to claim 12 , wherein
the ith-stage cascade circuit comprises a redundant amplifier; and the redundant amplifier is a differential operational amplifier, wherein the differential operational amplifier is configured to amplify the residual voltage in the ith-stage cascaded circuit and output the ith amplified signal.
14 . A residual voltage generation method, comprising the following steps:
converting, by a common mode voltage ADC, a common mode voltage of an input signal into a first digital signal;
converting, by an ADC, the input signal into a second digital signal;
receiving, by a digital signal processing module, the first digital signal and the second digital signal, and outputting a third digital signal and a fourth digital signal; and
receiving, by a sub-DAC, the input signal and a switching control signal generated based on the third digital signal and the fourth digital signal, and outputting a residual voltage;
wherein based on the third digital signal and the fourth digital signal, a common mode voltage of the residual voltage generated by the sub-DAC is approximately equal to a set threshold voltage.
15 . The residual voltage generation method according to claim 14 , wherein the step of receiving, by the digital signal processing module, the first digital signal and the second digital signal, and outputting the third digital signal and the fourth digital signal comprises:
when a number of bits of the first digital signal is equal to a number of bits of the second digital signal, the third digital signal is equal to a difference by subtracting a binary value corresponding to 2{circumflex over ( )}(N1-1) from a sum of the first digital signal and the second digital signal; the fourth digital signal is equal to a difference by subtracting the second digital signal from a sum of a binary value corresponding to (2{circumflex over ( )}(N1-1)−1) and the first digital signal; and N1 denotes the number of bits of the second digital signal; and
when the number of bits of the first digital signal is not equal to the number of bits of the second digital signal, the digital signal processing module comprises a number-of-bits conversion module for converting the number of bits of the first digital signal to be equal to the number of bits of the second digital signal; wherein the third digital signal is equal to a difference by subtracting the binary value corresponding to 2{circumflex over ( )}(N1-1) from a sum of the first digital signal converted to hold N1 bits and the second digital signal; and the fourth digital signal is equal to a difference by subtracting the second digital signal from a sum of the binary value corresponding to (2{circumflex over ( )}(N1-1)−1) and the first digital signal converted to hold N1 bits.
16 . The residual voltage generation method according to claim 15 , wherein
a difference between the third digital signal and the fourth digital signal is defined as a first difference;
the digital signal processing module is configured to limit decimal values corresponding to the third digital signal and the fourth digital signal to a range of 0 to (2{circumflex over ( )}N1-1);
when the decimal value corresponding to the third digital signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the decimal value corresponding to the third digital signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged; and
when the decimal value corresponding to the fourth digital signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the decimal value corresponding to the fourth digital signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged.
17 . The residual voltage generation method according to claim 14 , wherein the step of receiving, by the digital signal processing module, the first digital signal and the second digital signal, and outputting the third digital signal and the fourth digital signal comprises: outputting, by the first digital conversion module, a first conversion signal based on the first digital signal, and outputting a second conversion signal based on the second digital signal;
outputting, by a codeword transfer module, a third conversion signal and a fourth conversion signal based on the first conversion signal and the second conversion signal, and making a sum of the third conversion signal and the fourth conversion signal approximately twice the first conversion signal and a decimal difference between the third conversion signal and the fourth conversion signal equal to a difference between a double of a decimal value of the second conversion signal and (2{circumflex over ( )}N1-1), wherein N1 denotes a number of bits of the second digital signal; and
outputting, by a second digital conversion module, the third digital signal based on the third conversion signal, and outputting the fourth digital signal based on the fourth conversion signal.
18 . The residual voltage generation method according to claim 17 , wherein
when the first to fourth conversion signals are decimal signals,
the third conversion signal is equal to a difference by subtracting (2{circumflex over ( )}N1-1) from a sum of the second conversion signal and the first conversion signal; and
the fourth conversion signal is equal to a difference by subtracting the second conversion signal from a sum of (2{circumflex over ( )}(N1-1)−1) and the first conversion signal.
19 . The residual voltage generation method according to claim 18 , wherein
a difference between the third conversion signal and the fourth conversion signal is defined as a first difference;
the codeword transfer module is configured to limit the third conversion signal and the fourth conversion signal to a range of 0 to (2{circumflex over ( )}N1-1);
when the third conversion signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the third conversion signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged; and
when the fourth conversion signal is less than 0 or greater than (2{circumflex over ( )}N1-1), the fourth conversion signal is shifted into the range of 0 to (2{circumflex over ( )}N1-1), and the first difference remains unchanged.
20 . The residual voltage generation method according to claim 14 , wherein the set threshold voltage is half of a reference voltage.