Gate driver and display device including the same
A gate driver includes first to n th stages. A k th stage among the first to n th stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.
1 . A gate driver, comprising:
first to n th (n is a natural number greater than 2) stages, a k th (k is a natural number greater than 1 and less than n) stage among the first to n th stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.
2 . The gate driver of claim 1 , wherein the fourth transistor is a P-type transistor.
3 . The gate driver of claim 1 , wherein a threshold voltage of the fourth transistor is negatively shifted in a period in which the first control node or the second control node of the k−1 th stage has the high gate voltage and the inverting control node of the k+1 th stage has the low gate voltage.
4 . The gate driver of claim 1 , wherein the seventh transistor is a P-type transistor.
5 . The gate driver of claim 1 , wherein the k th stage further includes
a second transistor including a gate electrically connected to the second control node, a first terminal which receives the low gate voltage, and a second terminal electrically connected to the inverting control node.
6 . The gate driver of claim 5 , wherein the k th stage further includes:
a third transistor including a gate electrically connected to the first control node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the inverting control node.
7 . The gate driver of claim 6 , wherein:
the second transistor is an N-type transistor; and
the third transistor is a P-type transistor.
8 . The gate driver of claim 1 , wherein the k th stage further includes:
a first capacitor including a first terminal electrically connected to the second control node and a second terminal electrically connected to the output node; and
a second capacitor including a first terminal which receives the high gate voltage and a second terminal electrically connected to the inverting control node.
9 . A gate driver, comprising:
first to n th (n is a natural number greater than 2) stages, a k th (k is a natural number greater than 1 and less than n) stage among the first to n th stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k−1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k+1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.
10 . The gate driver of claim 9 , wherein the fourth transistor is a P-type transistor.
11 . The gate driver of claim 9 , wherein a threshold voltage of the fourth transistor is negatively shifted in a period in which the first control node or the second control node of the k+1 th stage has the high gate voltage and the inverting control node of the k−1 th stage has the low gate voltage.
12 . The gate driver of claim 9 , wherein the seventh transistor is a P-type transistor.
13 . The gate driver of claim 9 , wherein the k th stage further includes:
a second transistor including a gate electrically connected to the second control node, a first terminal which receives the low gate voltage, and a second terminal electrically connected to the inverting control node.
14 . The gate driver of claim 13 , wherein the k th stage further includes:
a third transistor including a gate electrically connected to the first control node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the inverting control node.
15 . The gate driver of claim 14 , wherein:
the second transistor is an N-type transistor; and
the third transistor is a P-type transistor.
16 . The gate driver of claim 9 , wherein the k th stage further includes:
a first capacitor including a first terminal electrically connected to the second control node and a second terminal electrically connected to the output node; and
a second capacitor including a first terminal which receives the high gate voltage and a second terminal electrically connected to the inverting control node.
17 . A display device, comprising:
a display panel including pixels;
a data driver which provides data signals to the pixels; and
a gate driver including first to n th (n is a natural number greater than 2) stages which provide first to n th gate signals to the pixels, a k th (k is a natural number greater than 1 and less than n) stage among the first to n th stages including:
a first transistor including a gate which receives a clock signal, a first terminal which receives an input signal, and a second terminal electrically connected to a first control node;
a fifth transistor including a gate electrically connected to an inverting control node, a first terminal which receives a high gate voltage, and a second terminal electrically connected to an output node outputting a gate signal;
a sixth transistor including a gate electrically connected to a second control node, a first terminal which receives a low gate voltage, and a second terminal electrically connected to the output node;
a fourth transistor including a gate which receives the low gate voltage, a first terminal electrically connected to the first control node, a second terminal electrically connected to the second control node, and a back gate; and
a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1 th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1 th stage, and a second terminal electrically connected to the back gate of the fourth transistor.
18 . The display device of claim 17 , wherein each of the pixels includes:
a driving transistor including a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node;
a write transistor including a gate which receives a write gate signal, a first terminal which receives at least one of the data signals, and a second terminal electrically connected to the second node;
a compensation transistor including a gate which receives a compensation gate signal, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node;
an initialization transistor including a gate which receives an initialization gate signal, a first terminal which receives a first initialization voltage, and a second terminal electrically connected to the first node;
a first emission transistor including a gate which receives an emission signal, a first terminal which receives a first power voltage, and a second terminal electrically connected to the second node;
a second emission transistor including a gate which receives the emission signal, a first terminal electrically connected to the third node, and a second terminal electrically connected to a fourth node;
a bypass transistor including a gate which receives a bypass gate signal, a first terminal which receives a second initialization voltage, and a second terminal electrically connected to the fourth node;
a bias transistor including a gate which receives the bypass gate signal, a first terminal which receives a bias voltage, and a second terminal electrically connected to the second node;
a storage capacitor including a first terminal which receives the first power voltage and a second terminal electrically connected to the first node; and
a light emitting element including a first terminal electrically connected to the fourth node and a second terminal which receives a second power voltage.
19 . The display device of claim 18 , wherein k th gate signal is one of the compensation gate signal, the initialization gate signal, the emission signal, and the bypass gate signal.
20 . The display device of claim 17 , wherein the fourth transistor is a P-type transistor.
21 . The display device of claim 17 , wherein the k th stage further includes:
a second transistor including a gate electrically connected to the second control node, a first terminal which receives the low gate voltage, and a second terminal electrically connected to the inverting control node; and
a third transistor including a gate electrically connected to the first control node, a first terminal which receives the high gate voltage, and a second terminal electrically connected to the inverting control node.