IP Library Patent Application 18983482
Patent Application
App. No. 18/983,482

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR CIRCUIT, METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR CIRCUIT

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Patent No.
US None
App. No.
18/983,482
Abstract

Disclosed is a complementary metal-oxide semiconductor circuit including a n-type metal-oxide semiconductor thin-film transistor and a p-type metal-oxide semiconductor thin-film transistor. Each of the n-type metal-oxide semiconductor thin-film transistor and the p-type metal-oxide semiconductor thin-film transistor includes a semiconductor film, a gate insulating film over the semiconductor film, a gate electrode over the gate insulating film, an interlayer insulating film over the gate electrode, and a pair of terminals located over the interlayer insulating film and electrically connected to the semiconductor film. The semiconductor film of the p-type metal-oxide semiconductor thin-film transistor includes a fluorine ion.

Claims (60)

1 . A complementary metal-oxide semiconductor circuit comprising:

a n-type metal-oxide semiconductor thin-film transistor and a p-type metal-oxide semiconductor thin-film transistor each comprising:

a semiconductor film;

a gate insulating film over the semiconductor film;

a gate electrode over the gate insulating film;

an interlayer insulating film over the gate electrode; and

a pair of terminals located over the interlayer insulating film and electrically connected to the semiconductor film,

wherein the semiconductor film of the p-type metal-oxide semiconductor thin-film transistor includes a fluorine ion.

2 . The complementary metal-oxide semiconductor circuit according to claim 1 ,

wherein, in each of the n-type metal-oxide semiconductor thin-film transistor and the p-type metal-oxide semiconductor thin-film transistor, the semiconductor film comprises:

a channel region overlapping the gate electrode;

a pair of low-concentration impurity regions sandwiching the channel region; and

a pair of source/drain regions sandwiching the pair of low-concentration impurity regions.

3 . The complementary metal-oxide semiconductor circuit according to claim 1 ,

wherein a concentration of the fluorine ion in the semiconductor film of the p-type metal-oxide semiconductor thin-film transistor is equal to or greater than 1×10 15 atoms/cm 3 and equal to or less than 1×10 20 atoms/cm 3 .

4 . The complementary metal-oxide semiconductor circuit according to claim 2 ,

wherein the fluorine ion is selectively included in the source/drain regions of the p-type metal-oxide semiconductor thin-film transistor.

5 . The complementary metal-oxide semiconductor circuit according to claim 1 , further comprising an undercoat under the n-type metal-oxide semiconductor thin-film transistor and the p-type metal-oxide semiconductor thin-film transistor,

wherein the undercoat includes the fluorine ion.

6 . An electronic device comprising a complementary metal-oxide semiconductor circuit comprising a n-type metal-oxide semiconductor thin-film transistor and a p-type metal-oxide semiconductor thin-film transistor each comprising:

a semiconductor film;

a gate insulating film over the semiconductor film;

a gate electrode over the gate insulating film;

an interlayer insulating film over the gate electrode; and

a pair or terminals located over the interlayer insulating film and electrically connected to the semiconductor film,

wherein the semiconductor film of the p-type metal-oxide semiconductor thin-film transistor includes a fluorine ion.

7 . The electronic device according to claim 6 ,

wherein, in each of the n-type metal-oxide semiconductor thin-film transistor and the p-type metal-oxide semiconductor thin-film transistor, the semiconductor film comprises:

a channel region overlapping the gate electrode;

a pair of low-concentration impurity regions sandwiching the channel region; and

a pair of source/drain regions sandwiching the pair of low-concentration impurity regions.

8 . The electronic device according to claim 6 ,

wherein a concentration of the fluorine ion in the semiconductor film of the p-type metal-oxide semiconductor thin-film transistor is equal to or greater than 1×10 15 atoms/cm 3 and equal to or less than 1×10 20 atoms/cm 3 .

9 . The electronic device according to claim 7 ,

wherein the fluorine ion is selectively included in the source/drain regions of the p-type metal-oxide semiconductor thin-film transistor.

10 . The electronic device according to claim 6 , further comprising an undercoat under the n-type metal-oxide semiconductor thin-film transistor and the p-type metal-oxide semiconductor thin-film transistor,

wherein the undercoat includes the fluorine ion.

11 . The electronic device according to claim 6 ,

wherein the electronic device is a display device.

12 . A fabrication method of a complementary metal-oxide semiconductor circuit, the fabrication method comprising:

forming an undercoat over a substrate;

forming a first semiconductor film and a second semiconductor film over the undercoat;

doping both edge portions of the first semiconductor film with a first dopant imparting n-type conductivity in a state where the second semiconductor film and a region between both the edge portions of the first semiconductor film are masked;

doping both edge portions of the second semiconductor film with a second dopant imparting p-type conductivity in a state where the first semiconductor film and a region between both the edge portions of the second semiconductor film are masked;

forming a gate insulating film over the first semiconductor film and the second semiconductor film;

forming, over the gate insulating film, a first gate electrode overlapping the first semiconductor film and exposing both the edge portions of the first semiconductor film and a second gate electrode overlapping the second semiconductor film and exposing both the edge portions of the second semiconductor film;

forming an interlayer insulating film overlapping the first gate electrode and the second gate electrode; and

forming, over the interlayer insulating film, a pair of electrodes electrically connected to the first semiconductor film and a pair of electrodes electrically connected to the second semiconductor film.

13 . The fabrication method according to claim 12 ,

wherein the second dopant includes boron and fluorine.

14 . The fabrication method according to claim 12 ,

wherein the second dopant includes at least one of a BF 2+ ion and a BF 2 + ion.

15 . The fabrication method according to claim 12 , further comprising:

doping the first semiconductor film with a third dopant imparting n-type conductivity using the first gate electrode as a mask; and

doping the second semiconductor film with a fourth dopant imparting p-type conductivity using the second gate electrode as a mask.

16 . The fabrication method according to claim 15 ,

wherein the third dopant and the fourth dopant are the same as each other.

17 . The fabrication method according to claim 12 , further comprising doping the first semiconductor film and the second semiconductor film with a fifth dopant imparting p-type conductivity before the doping with the first dopant and the second dopant.

18 . The fabrication method according to claim 13 ,

wherein the doping with the second dopant is performed such that a concentration of the fluorine ion in the second semiconductor film is equal to or greater than 1×10 15 atoms/cm 3 and equal to or less than 1×10 20 atoms/cm 3 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071599/0406 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2024
From: ITOGA, TOSHIHIKO
To: JAPAN DISPLAY INC.
Reel/Frame 069609/0143 →