IP Library › Granted Patent US 12,731,552
Granted Patent B2
US 12,731,552 · App. 18/990,111 · Granted Sep 8, 2026

Display device including a transistor that supplies current to a light emitting element being placed in on state before a voltage is stored in a storage capacitor

Inventors: Tetsuo Morita (Tokyo, JP); Kenji Harada (Tokyo, JP)
Assignee: MAGNOLIA WHITE CORPORATION
G09G3/3275G09G3/3266G09G2300/0842G09G2310/08
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Quick Facts
Patent No.
US 12,731,552
App. No.
18/990,111
Granted
Sep 8, 2026
Kind
B2
Abstract

A display device includes a base, pixels provided on the base, and a data signal line that supplies a data signal to each of the pixels. Each of the pixels includes a pixel circuit having a first transistor and a storage capacitor, and a light emitting element driven by the pixel circuit. A voltage that controls the current supplied to the light-emitting element is written to the storage capacitor. The first transistor is configured to supply a current to the light emitting element. One frame period for displaying one frame includes a second period for setting the first transistor in an on state, which is provided before a first period for writing a voltage to the storage capacitor.

Claims (42)

1 . A display device comprising:

a base;

a plurality of pixels provided in a display area on the base;

a data signal line supplying a data signal to each of the plurality of pixels;

a first power supply line for supplying a first voltage to each of the plurality of pixels; and

a second power supply line for supplying a second voltage to each of the plurality of pixels, wherein

each of the plurality of pixels includes;

a pixel circuit having a first transistor, a second transistor, and a storage capacitor, and

a light emitting element driven by the pixel circuit,

a voltage that controls a current supplied to the light emitting element is written to the storage capacitor,

the first transistor is configured to supply a current to the light emitting element, based on the voltage written to the storage capacitor,

one frame period for displaying one frame in the display area includes:

a first period,

a second period for setting the first transistor in an on state, which is provided before the first period, which is for writing a voltage corresponding to the data signal to the storage capacitor,

a third period for supplying a current to the light emitting element, which is provided after the first period, and

a fourth period for resetting a voltage written to the storage capacitor based on the first and second voltages supplied from the first and second power supply lines respectively,

the second period is between a third period included in one frame period before said one frame period and the first period included in said one frame period,

the second period is between the fourth period and the first period,

one of a source terminal and a drain terminal of the second transistor is connected to one of a source terminal and a drain terminal of the first transistor,

the other of the source terminal and the drain terminal of the second transistor is connected to a gate terminal of the first transistor and a first terminal of the storage capacitor,

the first voltage is supplied from the first power supply line to the first terminal of the storage capacitor,

the second voltage is supplied from the second power supply line to a second terminal of the storage capacitor, and

the second transistor becomes in an on state during the fourth period and the first period, and becomes in an off state during the second period.

2 . The display device of claim 1 , wherein

the second voltage is supplied to one of a source terminal and a drain terminal of the first transistor during the second period.

3 . The display device of claim 2 , further comprising:

a third power supply line for supplying a third voltage to each of the plurality of pixels, wherein

the pixel circuit includes third to fifth transistors,

one of a source terminal and a drain terminal of the third transistor is connected to the third power supply line,

the other of the source terminal and the drain terminal of the third transistor is connected to one of the source terminal and the drain terminal of the first transistor,

one of a source terminal and a drain terminal of the fourth transistor is connected to the other of the source terminal and the drain terminal of the first transistor,

the other of the source terminal and the drain terminal of the fourth transistor is connected to the light emitting element and one of a source terminal and a drain terminal of the fifth transistor,

one of the source terminal and the drain terminal of the fifth transistor is further connected to the second terminal of the storage capacitor,

the other of the source terminal and the drain terminal of the fifth transistor is connected to the second power supply line,

the third transistor is in an off state during the fourth period, the second period, and the first period, and is in an on state during the third period,

the fourth transistor is in an off state during the fourth period and the first period, and is in an on state during the second period and the third period, and

the fifth transistor is in an off state during the second period and the third period, and is in an on state during the fourth period and the first period.

4 . The display device of claim 3 , further comprising:

a first control signal line for supplying a first control signal to each of the plurality of pixels; and

a second control signal line for supplying a second control signal to each of the plurality of pixels,

the off state and the on state of the third transistor are controlled based on the first control signal, and

the off state and the on state of the fourth and fifth transistors are controlled based on the second control signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071759/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2024
From: MORITA, TETSUO; HARADA, KENJI
To: JAPAN DISPLAY INC.
Reel/Frame 069654/0193 →
Priority Claims (1)
JP 2023-214905 · Dec 20, 2023 · national
Continuity (1)
Related Publication 20250209997A1 · Jun 26, 2025
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