CIRCUITS AND METHOD FOR FAST, ENERGY EFFICIENT 6T SRAM ARRAYS USING HARVESTED DATA
A transistor memory device includes transistor storage elements storing a capacitance at each transistor storage element. Each transistor storage element includes a word line port that selects a bitcell and a bitline. Each transistor storage element performs a read data access from or a write data access to each remaining transistor storage element to increase a SNM. The device includes a harvest node configured to store a harvested charge transferred from the bitline. The transistor memory device includes a capacitor divider between the bitline and the harvest node of a first transistor storage element and configured to maintain a voltage swing on the bitline. The device further includes a harvest circuit configured to, in response to the read data access performed by the first transistor storage element, decouple the harvest node from a ground and invert a voltage equal to a potential difference between the bitline and the harvest node.
1 . (canceled)
2 . A transistor memory device, comprising:
a complementary metal-oxide-semiconductor (CMOS) inverter with a gate input terminal, a supply voltage terminal, a ground terminal, and an output terminal, the ground terminal configured to be coupled to a reference ground terminal of the transistor memory device via a field-effect transistor, a change in a first voltage signal configured to be developed by a transistor storage element at the gate input terminal during a read data access in which (1) the ground terminal is decoupled from the reference ground terminal and (2) the field-effect transistor is in an off state, a second voltage signal that is of opposite polarity to the first voltage signal configured to change at the ground terminal, the ground terminal configured to reset to a reference ground potential of the transistor memory device (1) by activation of the field-effect transistor via an activating pulse at a gate input of the field-effect transistor, (2) before the first voltage signal is developed by the transistor storage element, and (3) before the second voltage signal is changed at the ground terminal.
3 . The transistor memory device of claim 2 , wherein:
the transistor storage element includes (1) at least one word line terminal that is activated to select the transistor storage element for the read data access (2) at least one bitline terminal that develops a voltage or current signal in response to the transistor storage element being selected for the read data access and (3) a source terminal configured to develop the second voltage signal.
4 . The transistor memory device of claim 2 , further comprising:
a first plurality of transistor storage elements that share a common bitline terminal, a second plurality of transistor storage elements being a subset from the first plurality of transistor storage elements sharing a common source terminal; and
a third plurality of transistor storage elements that share a common word line terminal, each transistor storage element from the third plurality of transistor storage elements is (1) a transistor storage element from the first plurality of transistor storage elements and (2) a transistor storage element from the second plurality of transistor storage elements.
5 . The transistor memory device of claim 4 , wherein:
the common bitline terminal is coupled to the gate input terminal,
the common source terminal is a harvest node,
the common source terminal is coupled to the ground terminal of the CMOS inverter, and
the source terminal of the transistor storage element is configured to electrically decouple from the reference ground potential during the read data access.
6 . The transistor memory device of claim 5 , further comprising:
a capacitive divider electrically connected between the common bitline terminal and the common source terminal, the common bitline terminal having a capacitance proportional to a number of transistor storage elements in the first plurality of storage elements, a capacitance of the common source terminal proportional to a number of transistor storage elements in the second plurality of transistor storage elements.
7 . The transistor memory device of claim 6 , wherein:
a magnitude of a voltage signal developed on the common source terminal relative to a magnitude of a voltage signal developed on the common bitline terminal is determined by the capacitive divider between the common bitline terminal and the common source terminal.
8 . The transistor memory device of claim 7 , wherein:
the capacitive divider is configured to increase the voltage signal at the common source terminal to be within a predefined limit to retain data in the first plurality of transistor storage elements and the second plurality of transistor storage elements.
9 . The transistor memory device of claim 8 , wherein:
increasing the voltage signal at the common source terminal (1) increases an effective signal development rate asserted between the gate input terminal and the ground terminal of the CMOS inverter, (2) lowers an active energy of the read data access by allowing the transistor storage element to develop a smaller voltage signal at the common bitline terminal and (3) lowers a voltage difference between transistor storage element terminals improving a reliability degradation from a voltage accelerated aging mechanisms.
10 . The transistor memory device of claim 9 , wherein the transistor memory device is configured to resolve data in a subthreshold region where the CMOS inverter maintains larger than unity gain, the CMOS inverter configured to quantize binary signals with the capacitive divider enabling an increased voltage signal development rate at the common source terminal.
11 . The transistor memory device of claim 10 , wherein:
the field-effect transistor is a first field-effect transistor, the common bitline terminal is configured to be precharged to at least one of a supply voltage of the transistor memory device or to logic 1 in response to coupling the common bitline terminal to the supply voltage terminal through a second field-effect transistor (1) during the read data access and (2) before a transistor storage element in the first plurality of transistor storage elements is selected by activating the common word line terminal.
12 . The transistor memory device of claim 11 , wherein:
in response to precharging the common bitline terminal to the at least one of the supply voltage of the transistor memory device or to the logic 1, the common bitline terminal is configured to be decoupled from the supply voltage terminal of the CMOS inverter while the supply voltage terminal is held at the supply voltage.
13 . The transistor memory device of claim 12 , wherein:
the transistor storage element in the first plurality of transistor storage elements selected by activating the common word line terminal is configured to drain charge on the common bitline terminal by lowering a voltage at the common bitline terminal from the supply voltage.
14 . The transistor memory device of claim 13 , wherein:
the charge drained from the common bitline terminal is configured to be collected at the common source terminal during the read data access and raise an electric potential of the common source terminal.
15 . The transistor memory device of claim 14 , wherein:
raising the electric potential of the common source terminal and lowering the voltage at the common bitline terminal (1) self-limits a flow of current from the common bitline terminal to the common source terminal and (2) self-disables current flow when the voltage at the common bitline terminal is within a predetermined range of a metal-oxide-semiconductor field-effect transistor threshold voltage and above the common source terminal, a read current disabled while word line terminal is active to lower an energy and latency overhead.
16 . The transistor memory device of claim 15 , wherein:
the common source terminal at an elevated electric potential reverse biases a source body junction of an n-channel metal-oxide-semiconductor (NMOS) transistor at the transistor storage element for at least one transistor whose source terminal is coupled to the common source terminal and whose body terminal is coupled to the reference ground potential, the reverse biases at the source body junction enabling a reduction in a subthreshold leakage of the NMOS transistor.
17 . The transistor memory device of claim 13 , wherein:
the CMOS inverter does not use a sense amp enable signal and reduces latency overhead, energy overhead, and area overhead, the output terminal configured to self-trigger a low-to-high transition at the output terminal in response to a decreasing voltage at the gate input terminal being substantially equal to a rising trip voltage of the CMOS inverter.
18 . The transistor memory device of claim 14 , wherein:
the voltage signal developed on the common bitline terminal is determined by the capacitive divider, a voltage swing at the common bitline terminal fixed by the capacitive divider.