LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
1 . A multichip package comprising:
a first integrated-circuit (IC) chip;
a second integrated-circuit (IC) chip; and
an input/output (I/O) chip comprising a first input/output (I/O) circuit coupling to an external circuit of the multichip package and a plurality of second input/output (I/O) circuits coupling to the first and second integrated-circuit (IC) chips, wherein the first input/output (I/O) circuit has an input capacitance larger than that of each of the plurality of second input/output (I/O) circuits.
2 . The multichip package of claim 1 , wherein each of the first and second integrated-circuit (IC) chips comprises a third input/output (I/O) circuit coupling to one of the plurality of second input/output (I/O) circuits, wherein the input capacitance of the first input/output (I/O) circuit is larger than that of the third input/output (I/O) circuit.
3 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a third input/output (I/O) circuit coupling to a fourth input/output (I/O) circuit of the second integrated-circuit (IC) chip, wherein the input capacitance of the first input/output (I/O) circuit is larger than that of each of the third and fourth input/output (I/O) circuits.
4 . The multichip package of claim 3 , wherein each of the first and second integrated-circuit (IC) chips comprises a field programmable circuit.
5 . The multichip package of claim 1 comprising a third input/output (I/O) circuit for coupling between the first and second integrated-circuit (IC) chips, wherein the input capacitance of the first input/output (I/O) circuit is larger than that of the third input/output (I/O) circuit.
6 . The multichip package of claim 1 , wherein each of the first and second integrated-circuit (IC) chips comprises a graphic processing unit (GPU).
7 . The multichip package of claim 1 , wherein each of the first and second integrated-circuit (IC) chips is a logic chip.
8 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a graphic processing unit (GPU) and the second integrated-circuit (IC) chip is a memory chip.
9 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a logic chip and the second integrated-circuit (IC) chip is a memory chip.
10 . The multichip package of claim 1 , wherein each of the first and second integrated-circuit (IC) chips has an area between 100 mm2 and 16 mm2.
11 . The multichip package of claim 1 , wherein each of the first and second integrated-circuit (IC) chips has an area between 50 mm2 and 16 mm2.
12 . The multichip package of claim 1 , wherein the input/output (I/O) chip comprises a plurality of third input/output (I/O) circuits having the first input/output (I/O) circuit, wherein the plurality of third input/output (I/O) circuits are configured to couple to the external circuit having a peripheral component interconnect express (PCIe) port.
13 . The multichip package of claim 1 , wherein the input/output (I/O) chip comprises a plurality of third input/output (I/O) circuits having the first input/output (I/O) circuit, wherein the plurality of third input/output (I/O) circuits are configured to couple to the external circuit having an Ethernet port.
14 . The multichip package of claim 1 , wherein the input capacitance of the first input/output (I/O) circuit is greater than 2 pF.
15 . The multichip package of claim 1 , wherein the input capacitance of each of the plurality of second input/output (I/O) circuits is smaller than 2 pF.
16 . The multichip package of claim 1 , wherein the input capacitance of each of the plurality of second input/output (I/O) circuits is smaller than 1 pF.
17 . The multichip package of claim 1 further comprising an interconnection scheme over the first and second integrated-circuit (IC) chips and input/output (I/O) chip, wherein the input/output (I/O) chip has a metal contact at its top and coupling to the interconnection scheme.
18 . The multichip package of claim 1 , wherein the first and second integrated-circuit (IC) chips and input/output (I/O) chip are at a same horizontal level.
19 . The multichip package of claim 16 further comprising:
a sealing layer at the same horizontal level as the first and second integrated-circuit (IC) chips and input/output (I/O) chip;
an interconnection scheme on a top surface of the sealing layer and over and coupling to the first and second integrated-circuit (IC) chips and input/output (I/O) chip; and
a metal bump at a top of the interconnection scheme, wherein the metal bump comprises tin.
20 . The multichip package of claim 19 , wherein each of the first and second integrated-circuit (IC) chips and input/output (I/O) chip comprises a metal contact coupling to the interconnection scheme and having a first copper layer at a top of said each of the first and second integrated-circuit (IC) chips and input/output (I/O) chip.
21 . The multichip package of claim 20 , the interconnection scheme comprises:
a polymer layer at a bottom of the interconnection scheme, wherein an opening in the polymer layer is vertically over the metal contact; and
an interconnection metal layer comprising a second copper layer in the opening and over a top surface of the polymer layer and an adhesion metal layer at a bottom of the second copper layer and in contact with a top surface of the metal contact.
22 . The multichip package of claim 21 , wherein the adhesion metal layer comprises titanium.
23 . The multichip package of claim 19 , wherein the sealing layer comprises a molding compound.
24 . The multichip package of claim 19 further comprising:
a ball-grid-array (BGA) substrate over the interconnection scheme and metal bump, wherein the ball-grid-array (BGA) substrate comprises a metal pad at a bottom of the ball-grid-array (BGA) substrate and joining the metal bump;
an underfill between the interconnection scheme and ball-grid-array (BGA) substrate and in contact with a sidewall of the metal bump; and
a plurality of solder balls on a top surface of the ball-grid-array (BGA) substrate and at a top of the chip package.