AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.
1 . A system, comprising:
a first sub-cache; and
a second sub-cache comprising:
a first cache line configured to store first data that corresponds to a write miss in the first sub-cache;
a memory configured to store a first value indicating whether the first cache line is half full; and
an eviction controller configured to:
determine whether the first cache line is half full based on the first value; and
based on a determination that the first cache line is half full, evict the first data stored in the first cache line.
2 . The system of claim 1 , wherein:
the second sub-cache further comprises a second cache line configured to store second data that correspond to a write miss in the first sub-cache;
the memory is further configured to store a second value indicating whether the second cache line is full; and
the eviction controller is further configured to:
determine whether the second cache line is full based on the second value; and
based on a determination that the second cache line is full, evict the second data stored in the second cache line.
3 . The system of claim 2 , wherein the memory is configured to store the first value in a first bit.
4 . The system of claim 2 , wherein the memory is configured to store the second value in a second bit.
5 . The system of claim 1 , wherein the second sub-cache is configured to store data evicted from the first sub-cache.
6 . The system of claim 1 , wherein the first sub-cache is a main cache, and the second sub-cache is a victim cache corresponding to the main cache.
7 . The system of claim 6 , wherein the first sub-cache is a level-one (L1) main cache, and the second sub-cache is a level-one (L1) victim cache.
8 . A method, comprising:
receiving, by a caching system including a first sub-cache and a second sub-cache, a first request to write first data;
determining, by the caching system, whether the first request corresponds to a miss in the first sub-cache;
based on determining that the first request corresponds to a miss in the first sub-cache,
storing the first data in a first cache line of the second sub-cache; and
storing a first value in the second sub-cache to indicate whether the first cache line is half full;
receiving a second request to evict a cache line of the second sub-cache; and
based on receiving the second request,
determining whether the first cache line of the second sub-cache is half full based on the first value; and
based on determining that the first cache line is half full, evicting the first data stored in the first cache line.
9 . The method of claim 8 , further comprising:
based on receiving the second request,
determining whether a second cache line of the second sub-cache is full based on a second value, wherein the second cache line stores second data that corresponds to a miss in the first sub-cache, and wherein the second value indicates whether the second cache line is full; and
based on determining that the second cache line is full, evicting the second data stored in the second cache line.
10 . The method of claim 9 , wherein the first value is a one-bit value.
11 . The method of claim 9 , wherein the second value is a one-bit value.
12 . The method of claim 8 , wherein the second sub-cache stores data evicted from the first sub-cache.
13 . The method of claim 8 , wherein the first sub-cache is a main cache, and the second sub-cache is a victim cache corresponding to the main cache.
14 . The method of claim 13 , wherein the first sub-cache is a level-one (L1) main cache, and the second sub-cache is a level-one (L1) victim cache.
15 . A device, comprising:
a processor configured to generate a first request to write first data;
a first sub-cache; and
a second sub-cache comprising:
a first cache line configured to store the first data, wherein the first data corresponds to a write miss in the first sub-cache;
a memory configured to store a first value indicating whether the first cache line is half full; and
an eviction controller configured to:
based on receiving a second request to evict a cache line of the second sub-cache,
determine whether the first cache line is half full based on the first value; and
based on a determination that the first cache line is half full, evict the first data stored in the first cache line.
16 . The device of claim 15 , wherein:
the second sub-cache further comprises a second cache line configured to store second data that corresponds to a write miss in the first sub-cache;
the memory is further configured to store a second value indicating whether the second cache line is full; and
the eviction controller is further configured to:
based on receiving the second request,
determine whether the second cache line is full; and
based on a determination that the second cache line is full, evict the second data stored in the second cache line.
17 . The device of claim 16 , wherein the first value is a one-bit value, and the second value is a one-bit value.
18 . The device of claim 15 , wherein the second sub-cache is configured to store data evicted from the first sub-cache.
19 . The device of claim 15 , wherein the first sub-cache is a main cache, and the second sub-cache is a victim cache corresponding to the main cache.
20 . The device of claim 19 , wherein the first sub-cache is a level-one (L1) main cache, and the second sub-cache is a level-one (L1) victim cache.