Equalizer with all-pass filter delay
The present disclosure describes an equalizer that uses an all-pass filter to delay a signal to a transconductor cell. According to an embodiment, the equalizer includes an input line, a first transconductor cell connected to the input line, a filter, and a second transconductor cell. The filter includes a first inverter connected to the input line, a second inverter connected to an output of the first inverter, and a third inverter connected to the input line and the output of the second inverter. The second transconductor cell is connected to the output of the second inverter.
1 . An equalizer comprising:
an input line;
a first transconductor cell connected to the input line;
a filter comprising:
a first inverter connected to the input line;
a second inverter connected to an output of the first inverter; and
a third inverter connected to the input line and the output of the second inverter; and
a second transconductor cell connected to the output of the second inverter.
2 . The equalizer of claim 1 , wherein the filter further comprises:
a first resistor connected to the output of the first inverter;
a capacitor connected to the output of the first inverter; and
a second resistor connected to the output of the second inverter.
3 . The equalizer of claim 2 , wherein the capacitor is programmable to adjust a delay of the filter.
4 . The equalizer of claim 1 , wherein:
the first inverter and the third inverter have a first transconductance; and
the second inverter has a second transconductance that is double the first transconductance.
5 . The equalizer of claim 1 , wherein:
the first inverter has a first transconductance;
the second inverter has a second transconductance that is double the first transconductance; and
the third inverter has a third transconductance that is half the first transconductance.
6 . The equalizer of claim 1 , wherein the second transconductor cell comprises the third inverter.
7 . The equalizer of claim 1 , wherein the first inverter comprises a fourth inverter and a fifth inverter and wherein a transconductance of the first inverter is adjusted by adjusting power to one or more of the fourth inverter or the fifth inverter.
8 . The equalizer of claim 1 , wherein the first transconductor cell comprises a fourth inverter.
9 . The equalizer of claim 1 , wherein the filter further comprises a shorted inverter connected to the output of the first inverter.
10 . A method comprising:
providing a transconductance using a first transconductor cell connected to an input line;
delaying, using a filter, a signal, wherein the filter comprises (i) a first inverter connected to the input line, (ii) a second inverter connected to an output of the first inverter, and (iii) a third inverter connected to the input line and the output of the second inverter; and
providing a transconductance using a second transconductor cell connected to the output of the second inverter.
11 . The method of claim 10 , wherein the filter further comprises:
a first resistor connected to the output of the first inverter;
a capacitor connected to the output of the first inverter; and
a second resistor connected to the output of the second inverter.
12 . The method of claim 10 , wherein:
the first inverter and the third inverter have a first transconductance; and
the second inverter has a second transconductance that is double the first transconductance.
13 . The method of claim 10 , wherein:
the first inverter has a first transconductance;
the second inverter has a second transconductance that is double the first transconductance; and
the third inverter has a third transconductance that is half the first transconductance.
14 . The method of claim 10 , wherein the second transconductor cell comprises the third inverter.
15 . The method of claim 10 , wherein the first inverter comprises a fourth inverter and a fifth inverter and wherein a transconductance of the first inverter is adjusted by adjusting power to one or more of the fourth inverter or the fifth inverter.
16 . The method of claim 10 , wherein the first transconductor cell comprises a fourth inverter.
17 . The method of claim 10 , wherein the filter further comprises a shorted inverter connected to the output of the first inverter.
18 . An equalizer comprising:
an input line;
a first transconductor cell of a main cursor of the equalizer;
an all-pass filter comprising:
a first inverter connected to the input line;
a second inverter connected to an output of the first inverter; and
a third inverter connected to the input line and the output of the second inverter, wherein the all-pass filter is arranged to delay a signal from the input line; and
a second transconductor cell of a post-cursor of the equalizer, wherein the second transconductor cell is connected to the output of the second inverter, and wherein the second transconductor cell is arranged to receive the signal from the all-pass filter.
19 . The equalizer of claim 18 , wherein the all-pass filter further comprises:
a first resistor connected to the output of the first inverter;
a capacitor connected to the output of the first inverter; and
a second resistor connected to the output of the second inverter.
20 . The equalizer of claim 18 , wherein:
the first inverter and the third inverter have a first transconductance; and
the second inverter has a second transconductance that is double the first transconductance.