LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
1 . A multichip package comprising:
a first integrated-circuit (IC) chip;
a second integrated-circuit (IC) chip comprising a first input/output (I/O) circuit coupling to an external circuit of the multichip package and a second input/output (I/O) circuit coupling to the first integrated-circuit (IC) chip, wherein the first input/output (I/O) circuit has an input capacitance larger than that of the second input/output (I/O) circuit, wherein the second integrated-circuit (IC) chip has a metal contact at its top, wherein the metal contact comprises a first copper layer having a thickness between 3 and 60 micrometers; and
an interconnection scheme over the first and second integrated-circuit (IC) chips and coupling to the metal contact of the second integrated-circuit (IC) chip.
2 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a third input/output (I/O) circuit coupling to the second input/output (I/O) circuits, wherein the input capacitance of the first input/output (I/O) circuit is larger than that of the third input/output (I/O) circuit.
3 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a field programmable circuit.
4 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a graphic processing unit (GPU).
5 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a memory chip.
6 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip is a logic chip.
7 . The multichip package of claim 1 , wherein the second integrated-circuit (IC) chip is an input/output (I/O) chip.
8 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip has an area between 100 mm 2 and 16 mm 2 .
9 . The multichip package of claim 1 , wherein the first integrated-circuit (IC) chip has an area between 50 mm 2 and 16 mm 2 .
10 . The multichip package of claim 1 , wherein the second integrated-circuit (IC) chip comprises a plurality of third input/output (I/O) circuits having the first input/output (I/O) circuit, wherein the plurality of third input/output (I/O) circuits are configured to couple to the external circuit having a peripheral component interconnect express (PCIe) port.
11 . The multichip package of claim 1 , wherein the second integrated-circuit (IC) chip comprises a plurality of third input/output (I/O) circuits having the first input/output (I/O) circuit, wherein the plurality of third input/output (I/O) circuits are configured to couple to the external circuit having an Ethernet port.
12 . The multichip package of claim 1 , wherein the input capacitance of the first input/output (I/O) circuit is greater than 2 pF.
13 . The multichip package of claim 1 , wherein the input capacitance of the second input/output (I/O) circuit is smaller than 2 pF.
14 . The multichip package of claim 1 , wherein the input capacitance of the second input/output (I/O) circuit is smaller than 1 pF.
15 . The multichip package of claim 1 , wherein the first and second integrated-circuit (IC) chip are at a same horizontal level, wherein the interconnection scheme further couples to the first integrated-circuit (IC) chip.
16 . The multichip package of claim 15 further comprising:
a sealing layer at the same horizontal level as the first and second integrated-circuit (IC) chips, wherein the interconnection scheme is on a top surface of the sealing layer; and
a metal bump at a top of the interconnection scheme, wherein the metal bump comprises tin.
17 . The multichip package of claim 16 , wherein the sealing layer comprises a molding compound.
18 . The multichip package of claim 16 further comprising:
a ball-grid-array (BGA) substrate over the interconnection scheme and metal bump, wherein the ball-grid-array (BGA) substrate comprises a metal pad at a bottom of the ball-grid-array (BGA) substrate and joining the metal bump;
an underfill between the interconnection scheme and ball-grid-array (BGA) substrate and in contact with a sidewall of the metal bump; and
a plurality of solder balls on a top surface of the ball-grid-array (BGA) substrate and at a top of the chip package.
19 . The multichip package of claim 1 , wherein the first copper layer of the metal contact is at a top of the second integrated-circuit (IC) chip.
20 . The multichip package of claim 1 , wherein the interconnection scheme comprises:
a polymer layer at a bottom of the interconnection scheme, wherein an opening in the polymer layer is vertically over the metal contact; and
an interconnection metal layer comprising a second copper layer in the opening and over a top surface of the polymer layer and an adhesion metal layer at a bottom of the second copper layer and in contact with a top surface of the metal contact.
21 . The multichip package of claim 20 , wherein the adhesion metal layer comprises titanium.