Methods of fabricating porous silicon structures
The present disclosure provides methods of manufacturing porous silicon structures having controlled sizes, shapes, and porosity by using a series of protective layers and selective etching steps. A benefit of the methods disclosed herein can be providing microfabrication and nanofabrication methods that are capable of provide porous silicon structures having sizes, shapes, and porosity that are more tightly controlled by avoiding inadvertently etching parts of the silicon structures during the fabrication process.
1 . A method of manufacturing porous silicon structures comprising:
providing a silicon substrate having a silicon surface, wherein the silicon substrate is a heavily doped p ++ type wafer with resistivity ranging from about 0.003 ohm-cm to about 0.007 ohm-cm;
forming a first protective layer on the silicon surface, wherein the first protective layer has a protective layer surface, wherein the first protective layer comprises silicon oxide;
depositing a second protective layer on the protective layer surface;
forming protected areas and non-protected areas on the first protective layer surface by patterning the second protective layer;
forming first protective layer pillars by performing a first etch of the non-protected areas of the first protective layer;
forming silicon pillars by performing a second etch of the silicon substrate, wherein the silicon pillars are located beneath the first protective layer pillars, wherein the silicon pillars have a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, and wherein adjacent silicon pillar sidewalls are separated by silicon trenches having a silicon pillar spacing,
covering the first protective layer pillars, the silicon pillar sidewalls, and the silicon trenches by depositing a dielectric layer;
patterning the dielectric layer by removing a portion of the dielectric layer from a top of the protective layer pillars by exposing the dielectric layer to a third etch; and
removing the protective layer pillars by exposing the protective layer pillars to a fourth etch.
2 . The method of claim 1 , further comprising:
forming porous silicon pillars by applying a current to the silicon substrate; or
forming porous silicon pillars by applying a current to the silicon substrate through a solution in an electrolytic cell, wherein the current has a current density of about 1 mA/cm 2 to about 50 mA/cm 2 .
3 . The method of claim 2 , further comprising:
forming porous silicon structures by removing the dielectric layer; or
forming porous silicon structures and separating the porous silicon structures from the silicon substrate by applying a current to the silicon substrate of from about 100 mA/cm 2 to about 200 mA/cm 2 while the silicon substrate is submerged in a fifth etch solution comprising HF.
4 . The method of claim 1 , wherein the silicon surface comprises boron; or
wherein the first protective layer comprises silicon oxide, aluminum oxide, chromium, nickel, copper, or any combination thereof; or
wherein the second protective layer comprises a photoresist; or
wherein dielectric layer comprises silicon nitride.
5 . The method of claim 1 , wherein the first protective pillars have a protective pillar width of from about 200 nm to about 5.0 micrometers and a protective pillar height of from about 100 nm to about 600 nm; or
wherein the first protective pillars have a protective pillar width of from about 600 nm to about 4.0 micrometers and a protective pillar height of from about 150 nm to about 500 nm.
6 . The method of claim 1 , wherein the silicon pillar height is from about 2.0 micrometers to about 50.0 micrometers, the silicon pillar width is from about 200 nm to about 5.0 micrometers and the silicon pillar spacing is from about 200 nm to about 1000 nm; or
wherein the silicon pillar height is from about 6.0 micrometers to about 15.0 micrometers, the silicon pillar width is from about 600 nm to about 4.0 micrometers, and the silicon pillar spacing is from about 300 nm to about 800 nm.
7 . The method of claim 1 , wherein a ratio of the silicon pillar height to silicon pillar spacing is from about 60:1 to about 20:1; or
wherein a ratio of the silicon pillar height to silicon pillar spacing is from about 55:1 to about 45:1.
8 . The method of claim 1 , wherein the first protective layer comprises silicon oxide and the first etch includes reactive ion etching under an atmosphere of CF 4 and/or CHF 3 , or exposing the non-protected areas of the first protective layer to a first etching solution comprising HF, NH 4 HF, NaF, KF, or any combination or mixture thereof; or
wherein the first protective layer comprises aluminum oxide and the first etch includes exposing the non-protected areas of the first protective layer to a first etching solution comprising HF, NH 4 OH, tetra-methylammonium hydroxide, H 3 PO, Br 2 , or any combination or mixture thereof; or
wherein the first protective layer comprises chromium and the first etch includes exposing the non-protected areas of the first protective layer to a first etching solution comprising H 2 O 2 , HCl, H 2 SO 4 and H 2 O 2 , or any combination or mixture thereof; or
wherein the first protective layer comprises nickel and the first etch exposing the non-protected areas of the first protective layer to a first etching solution comprising HNO 3 , FeCl 3 , Ce(NH 4 ) 2 (NO 3 ) 6 , HF and H 2 O 2 , H 3 PO 4 , or any combination or mixture thereof; or
wherein the first protective layer comprises copper and the first etch includes exposing the non-protected areas of the first protective layer to a first etching solution comprising HNO 3 , FeCl 3 , KCN, H 2 O 2 , or any combination or mixture thereof.
9 . The method of claim 1 , wherein the second etch comprises reactive ion etching; or wherein the second etch comprises inductively coupled plasma reactive ion etching; or
wherein the second etch comprises reactive ion etching under an atmosphere of SF 6 ; or
wherein the second etch comprises inductively coupled plasma reactive ion etching under an atmosphere of SF 6 .
10 . The method of claim 1 , wherein the third etch comprises reactive ion etching; or wherein the third etch comprises reactive ion etching under an atmosphere of CF 4 , CHF 3 , or SF 6 .
11 . The method of claim 1 , wherein the fourth etch includes exposing the first protective layer pillars to a fourth etching solution,
wherein the first protective layer pillars comprise silicon oxide and the fourth etch solution comprises HF, NH 4 HF, NaF, KF, or any combination or mixture thereof, or
wherein the first protective layer pillars comprise aluminum oxide and the fourth etch solution comprises HF, NH 4 OH, H 3 PO, Br 2 , or any combination or mixture thereof; or
wherein the first protective layer pillars comprise chromium and the fourth etch solution comprises NaOH, H 2 O 2 , HCl, or any combination or mixture thereof; or
wherein the first protective layer pillars comprises nickel and the fourth etch solution comprises HNO 3 , FeCl 3 , Ce(NH 4 ) 2 (NO 3 ) 6 , HF, H 3 PO 4 , or any combination or mixture thereof; or
wherein the first protective layer pillars comprise copper and the fourth etch solution comprises HNO 3 , FeCl 3 , KCN, H 2 O 2 , or any combination or mixture thereof; or
wherein the first etching solution and the second etching solution are the same or different.
12 . The method of claim 3 , wherein the porous silicon structures have a first end, second end, and a side, wherein at least one of the first face and the second face are planar or flat; or
wherein the porous silicon structures have a first end, second end, and a side, wherein at least one of the first face or the second face has a longest face measurement across the first face or the second face of about 500 nm to about 5.0 micrometers, or the side has a longest side measurement across the side of about 100 nm to about 800 nm or any combination thereof.
13 . The method of claim 3 , wherein from about 30% to 100% of the porous silicon structures in a sample are characterized as have a first end, second end, and a side, wherein at least one of the first face and the second face are planar or flat; or
wherein from about 30% to 100% of the porous silicon structures in a sample are characterized as have a first end, second end, and a side, wherein at least one of the first face or the second face has a longest face average measurement across the first face or the second face of about 500 nm to about 5.0 micrometers, or the side has a longest side average measurement across the side of about 100 nm to about 800 nm or any combination thereof.
14 . The method of claim 1 , wherein the first protective layer is deposited by chemical vapor deposition, physical vapor deposition, vacuum evaporation, sputtering, or heating the silicon substrate to a temperature of from about 800° C. to about 1,200° C.; or
wherein the second protective layer is deposited by spin-coating or spraying; or
wherein the dielectric layer is deposited by chemical vapor deposition.
15 . The method of claim 1 , wherein the fourth etch removes the protective layer pillars without causing distortion to the silicon pillar top.
16 . The method of claim 3 , wherein the porous silicon structures are formed without deformation of their shapes, sizes, or structural integrity.
17 . A method of manufacturing porous silicon structures comprising:
providing a silicon substrate having a silicon surface, wherein the silicon substrate is a heavily doped p ++ type wafer with resistivity ranging from about 0.003 ohm-cm to about 0.007 ohm-cm;
forming a first protective layer on the silicon surface, wherein the first protective layer has a protective layer surface, wherein the first protective layer comprises silicon oxide;
depositing a second protective layer on the protective layer surface;
forming protected areas and non-protected areas on the first protective layer surface by patterning the second protective layer;
forming first protective layer pillars by performing a first etch of the non-protected areas of the first protective layer;
forming silicon pillars by performing a second etch of the silicon substrate, wherein the silicon pillars are located beneath the first protective layer pillars, wherein the silicon pillars have a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, and wherein adjacent silicon pillar sidewalls are separated by silicon trenches having a silicon pillar spacing,
covering the first protective layer pillars, the silicon pillar sidewalls, and the silicon trenches by depositing a dielectric layer;
patterning the dielectric layer by removing a portion of the dielectric layer from a top of the protective layer pillars by exposing the dielectric layer to a third etch; and
removing the first protective layer pillars by exposing the protective layer pillars to a fourth etch;
wherein the third etch comprises reactive ion etching under an atmosphere of CF 4 , CHF 3 , or SF 6 ; and
wherein a ratio of the silicon pillar height to silicon pillar spacing is from about 60:1 to about 20:1.
18 . The method of claim 17 ,
wherein the first protective pillars have a protective pillar width of from about 200 nm to about 5.0 micrometers and a protective pillar height of from about 100 nm to about 600 nm;
wherein the silicon pillar height is from about 2.0 micrometers to about 50.0 micrometers, the silicon pillar width is from about 200 nm to about 5.0 micrometers and the silicon pillar spacing is from about 200 nm to about 1000 nm; and
wherein the second etch comprises reactive ion etching under an atmosphere of SF 6 .