IP Library › Granted Patent US 12,749,525
Granted Patent B2
US 12,749,525 · App. 19/014,280 · Granted Sep 29, 2026

Semiconductor device and method for manufacturing the same

Inventor: Kuo-Chiang Wang (Taoyuan City, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
G11C11/4093H10B12/09H10B12/50H10B80/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,749,525
App. No.
19/014,280
Granted
Sep 29, 2026
Kind
B2
Abstract

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a memory cell array, a memory interface, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit supports a first memory protocol, and the second peripheral circuit supports a second memory protocol different from the first memory protocol. The first peripheral circuit and the second peripheral circuit share the memory cell array and the memory interface.

Claims (9)

1 . A method for manufacturing a semiconductor device, comprising:

obtaining a plurality of memory chips that are fabricated on a silicon wafer using one set of masks, wherein each of the plurality of memory chips comprises a memory interface, an eFuse, a first peripheral circuit, a second peripheral circuit, and a memory cell array;

dividing the plurality of memory chips into a first category and a second category;

breaking the eFuse to disconnect the memory interface from the second peripheral circuit for each memory chip in the first category to support a first memory protocol; and

breaking the eFuse to disconnect the memory interface from the first peripheral circuit for each memory chip in the second category to support a second memory protocol,

wherein the second memory protocol is different from the first memory protocol.

2 . The method of claim 1 , wherein the first peripheral circuit and the second peripheral circuit share the memory cell array and the memory interface.

3 . The method of claim 1 , wherein the first memory protocol is LPDDR4 (Low-power Double Data Rate 4), and the second memory protocol is LPDDR4X (Low-power Double Data Rate 4X).

4 . The method of claim 1 , wherein the first memory protocol is LPDDR5 (Low-power Double Data Rate 5), and the second memory protocol is LPDDR5X (Low-power Double Data Rate 5X).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2025
From: WANG, KUO-CHIANG
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 069792/0474 →
Continuity (3)
Continuation 18380876 · Oct 17, 2023
Division 18111676 · Feb 20, 2023
Related Publication 20250149082A1 · May 8, 2025
References Cited (12)
US 9543952B2 · Lee · 2017 [cited by examiner]
US 10651979B1 · Katakwar · 2020 [cited by examiner]
US 11190188B2 · Cho · 2021 [cited by examiner]
US 20090168562A1 · Tsunetou · 2009 [cited by examiner]
US 20130038375A1 · Lin · 2013 [cited by examiner]
US 20160104788A1 · Ryu · 2016 [cited by examiner]
US 20180018913A1 · Kim · 2018 [cited by examiner]
US 20190259429A1 · Heo · 2019 [cited by examiner]
US 20220350749A1 · Artieri · 2022 [cited by examiner]
US 20230386590A1 · Yan · 2023 [cited by examiner]
US 20230386979A1 · Bautista · 2023 [cited by examiner]
Office Action and and the search report mailed on Mar. 10, 2025 related to U.S. Appl. No. 18/380,876, wherein this application is a CON of U.S. Appl. No. 18/380,876. [cited by applicant]