IP Library Granted Patent US 12,657,068
Granted Patent B2
US 12,657,068 · App. 19/030,316 · Granted Jun 16, 2026

Cluster computing

Inventors: Zvi Tannenbaum (Newport Coast, CA); Dean E. Dauger (Huntington Beach, CA)
Assignee: Advanced Cluster Systems, Inc.
G06F9/5072G06F9/54G06F15/76H04L41/04
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Quick Facts
Patent No.
US 12,657,068
App. No.
19/030,316
Granted
Jun 16, 2026
Kind
B2
Abstract

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

Claims (52)

1 . A system for gathering data, the system comprising:

a non-transitory computer-readable memory that stores program code; and

a hardware processor that is in communication with the non-transitory computer-readable memory and that executes the program code to at least:

execute a command to distribute values among a plurality of processing nodes at least partially in parallel, wherein the plurality of processing nodes coordinate tasks with each other;

wherein the plurality of processing nodes comprise:

a first processing node that, when executing the command: sends a first value stored in a first memory to the remaining processing nodes of the plurality of processing nodes; receives a first set of values from the remaining processing nodes of the plurality of processing nodes; and stores the first set of values in the first memory, wherein the first value is sent to the remaining processing nodes while the first set of values are being received;

a second processing node that, when executing the command: sends a second value stored in a second memory to the remaining processing nodes of the plurality of processing nodes; receives a second set of values from the remaining processing nodes of the plurality of processing nodes; and stores the second set of values in the second memory, wherein the second value is sent to the remaining processing nodes while the second set of values are being received; and

a third processing node that, when executing the command: sends a third value stored in a third memory to the remaining processing nodes of the plurality of processing nodes; receives a third set of values from the remaining processing nodes of the plurality of processing nodes; and stores the third set of values in the third memory, wherein the third value is sent to the remaining processing nodes while the third set of values are being received.

2 . The system of claim 1 , wherein the hardware processor implements the first processing node.

3 . The system of claim 1 , wherein the first processing node comprises a root node.

4 . The system of claim 1 , wherein the first processing node accesses a non-volatile memory to access program code that when executed by the first processing node causes the first processing node to communicate with the second processing node via a first communications interface using a peer-to-peer architecture, wherein the second processing node communicates with the third processing node via a second communications interface using the peer-to-peer architecture; and wherein the third processing node communicates with the first processing node via a third communications interface using the peer-to-peer architecture.

5 . The system of claim 4 , wherein the non-volatile memory comprises the non-transitory computer-readable memory and wherein the program code of the non-volatile memory comprises the program code of the non-transitory computer-readable memory.

6 . The system of claim 4 , wherein the non-volatile memory comprises the first memory.

7 . The system of claim 1 , wherein each of the first processing node, the second processing node, and the third processing node accesses the program code from the non-transitory computer-readable memory, wherein executing the program code causes each of the first processing node, the second processing node, and the third processing node to communicate with a respective adjacent processing node of the plurality of processing nodes via a peer-to-peer architecture.

8 . The system of claim 1 , wherein each of the plurality of processing nodes is implemented by a different hardware processor.

9 . The system of claim 2 , wherein each of the plurality of processing nodes is implemented on the same computer system.

10 . The system of claim 1 , wherein each of the plurality of processing nodes is implemented on a different computer system.

11 . The system of claim 1 , wherein the command comprises a gather command.

12 . The system of claim 1 , wherein the command causes the values to be distributed among the plurality of processing nodes in parallel.

13 . A system for reducing data, the system comprising:

a non-transitory computer-readable memory that stores program code; and

a hardware processor that is in communication with the non-transitory computer-readable memory and that executes the program code to at least:

execute a command to distribute a reduced value set among a plurality of processing nodes at least partially in parallel, wherein the plurality of processing nodes coordinate tasks with each other;

wherein the plurality of processing nodes comprise:

a first processing node that, when executing the command: combines a first value set with a second value set and a third value set to obtain a combined value set; executes a mathematical expression on the combined value set to obtain a reduced value set; distributes the reduced value set among the plurality of processing nodes; and stores a first data set corresponding to the reduced value set in a first memory of the first processing node;

a second processing node that, when executing the command: sends the second value set to the first processing node and receives a second data set corresponding to the reduced value set from the first processing node; and

a third processing node that, when executing the command: sends the third value set to the first processing node and receives a third data set corresponding to the reduced value set from the first processing node, wherein the third value set is sent to the first processing node at least partially in parallel with the second value set being sent to the first processing node, and wherein the third data set is received at least partially in parallel with the second data set being received by the second processing node.

14 . The system of claim 13 , wherein the hardware processor implements the first processing node, and wherein a second hardware processor implements the second processing node.

15 . The system of claim 13 , wherein the first data set, the second data set, and the third data set each comprise a copy of the reduced value set.

16 . The system of claim 13 , wherein the first data set comprises a first portion of the reduced value set, the second data set comprises a second portion of the reduced value set, and the third data set comprises a third portion of the reduced value set.

17 . The system of claim 13 , wherein the first processing node communicates with the second processing node via a peer-to-peer architecture.

18 . The system of claim 13 , wherein the plurality of processing nodes communicate with each other using a communications network that implements peer-to-peer communication.

19 . The system of claim 13 , wherein the command comprises a reduce command.

20 . The system of claim 13 , wherein the command causes the reduced value set to be distributed among the plurality of processing nodes in parallel.

21 . A system for distributing values, the system comprising:

a non-transitory computer-readable memory that stores program code; and

a hardware processor in communication with the non-transitory computer-readable memory and configured to execute the program code to at least:

execute a command to distribute values from a plurality of processing nodes among the plurality of processing nodes at least partially in parallel, wherein the plurality of processing nodes coordinate tasks with each other;

wherein the plurality of processing nodes comprise:

a first processing node that, when executing the command: sends a first portion of a first set of values stored in a first memory to a second processing node;

sends a second portion of the first set of values to a third processing node; receives a first portion of a second set of values from the second processing node; receives a first portion of a third set of values from the third processing node; and stores the first portion of the second set of values and the first portion of the third set of values in the first memory, wherein the first portion of the first set of values and the second portion of the first set of values are sent while the first portion of the second set of values and the first portion of the third set of values are being received;

the second processing node that, when executing the command: sends the first portion of the second set of values stored in a second memory to the first processing node; sends a second portion of the second set of values to the third processing node; receives the first portion of the first set of values from the first processing node; receives a second portion of the third set of values from the third processing node; and stores the first portion of the first set of values and the second portion of the third set of values in the second memory, wherein the first portion of the second set of values and the second portion of the second set of values are sent while the first portion of the first set of values and the second portion of the third set of values are being received; and

the third processing node that, when executing the command: sends the first portion of the third set of values stored in a third memory to the first processing node; sends the second portion of the third set of values to the second processing node; receives the second portion of the first set of values from the first processing node; receives the second portion of the second set of values from the second processing node; and stores the second portion of the first set of values and the second portion of the second set of values in the third memory, wherein the first portion of the third set of values and the second portion of the third set of values are sent while the second portion of the first set of values and the second portion of the second set of values are being received.

22 . The system of claim 21 , wherein, absent an additional command, a third portion of the first set of values continues to be stored at the first memory after execution of the command.

23 . The system of claim 21 , wherein the first portion of the first set of values, the second portion of the first set of values, and a third portion of the first set of values are of equal size.

24 . The system of claim 21 , wherein the first portion of the first set of values, the first portion of the second set of values, and the first portion of the third set of values are of equal size.

25 . The system of claim 21 , wherein the first processing node, the second processing node, and the third processing node form a node cluster among which sets of values are distributed in response to the command.

26 . The system of claim 21 , wherein the first processing node receives values from each processing node of the plurality of processing nodes.

27 . The system of claim 21 , wherein the first processing node sends at least a portion of the first set of values to each processing node of the plurality of processing nodes.

28 . The system of claim 21 , wherein the first processing node accesses a non-volatile memory to access program code that when executed by the first processing node causes the first processing node to communicate with the second processing node via a communications interface using a peer-to-peer architecture.

29 . The system of claim 21 , wherein the command comprises an all-to-all command.

30 . The system of claim 21 , wherein the command causes the values to be redistributed among the plurality of processing nodes in parallel such that the distribution of values after the command differs from the distribution of values before the command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2025
From: TANNENBAUM, ZVI; DAUGER, DEAN E.
To: ADVANCED CLUSTER SYSTEMS, INC.
Reel/Frame 072722/0094 →
Continuity (14)
Continuation 18666632 · May 16, 2024
Continuation 18479720 · Oct 2, 2023
Continuation 18158283 · Jan 23, 2023
Continuation 17374864 · Jul 13, 2021
Continuation 17374789 · Jul 13, 2021
Continuation 16449084 · Jun 21, 2019
Continuation 16449084 · Jun 21, 2019
Continuation 14181112 · Feb 14, 2014
Continuation 13423063 · Mar 16, 2012
Continuation 12040519 · Feb 29, 2008
Continuation In Part 11744461 · May 4, 2007
Provisional Application 60850908 · Oct 11, 2006
Provisional Application 60813738 · Jun 13, 2006
Related Publication 20250173196A1 · May 29, 2025
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