INTEGRATED IN-MEMORY COMPUTE CONFIGURED FOR EFFICIENT DATA INPUT AND RESHAPING
A compute engine (CE) is described. The CE includes a compute-in-memory (CIM) module and an input buffer coupled with the CIM module. The CIM module includes storage cells and compute logic coupled with the storage cells. The storage cells are arranged in rows and columns. The input buffer is configured to receive data, reshape the data, and provide reshaped data to the CIM module.
1 . A compute engine (CE), comprising:
a compute-in-memory (CIM) module including a plurality of storage cells and compute logic coupled with the plurality of storage cells, the plurality of storage cells being arranged in a plurality of rows and a plurality of columns; and
an input buffer coupled with the CIM module and configured to receive data, reshape the data, and provide reshaped data to the CIM module.
2 . The CE of claim 1 , wherein the input buffer includes a plurality of shift registers configured to bit-wise transpose the data.
3 . The CE of claim 1 , wherein the data is bit-parallel and the input buffer bit-serializes the data.
4 . The CE of claim 1 , wherein a source of the data is clocked at a first frequency and the CIM module is clocked at a second frequency.
5 . The CE of claim 4 , wherein the input buffer is configured to convert the first frequency to the second frequency.
6 . The CE of claim 4 , wherein the first frequency is a multiple of the second frequency.
7 . The CE of claim 1 , wherein the input buffer includes at least one bank and wherein a portion of the data in each of the at least one bank is loaded to the CIM module in parallel.
8 . The CE of claim 7 , further comprising:
a demultiplexer configured to route a portion of the data to a bank of the at least one bank.
9 . A compute tile, comprising:
at least one general-purpose (GP) processor; and
a plurality of compute engines (CEs), each of the plurality of CEs including a compute-in-memory (CIM) module and an input buffer coupled to the CIM module, the CIM module including a plurality of storage cells and compute logic coupled with the plurality of storage cells, the plurality of storage cells being arranged in a plurality of rows and a plurality of columns, the an input buffer being configured to receive data, reshape the data, and provide reshaped data to the CIM module.
10 . The compute tile of claim 9 , wherein the input buffer includes a plurality of shift registers configured to bit-wise transpose the data.
11 . The compute tile of claim 9 , wherein the data is bit-parallel and the input buffer bit-serializes the data.
12 . The compute tile of claim 9 , wherein a source of the data is clocked at a first frequency and the CIM module is clocked at a second frequency.
13 . The compute tile of claim 12 , wherein the source of the data is the at least one GP processor.
14 . The compute tile of claim 12 , wherein the input buffer is configured to convert the first frequency to the second frequency.
15 . The compute tile of claim 12 , wherein the first frequency is a multiple of the second frequency.
16 . The compute tile of claim 9 , wherein the input buffer includes at least one bank and wherein a portion of the data in each of the at least one bank is loaded to the CIM module in parallel.
17 . A method, comprising:
receiving, at an input buffer of a compute engine (CE), data for a compute-in-memory (CIM) module of the CE, the CIM module including a plurality of storage cells and compute logic coupled with the plurality of storage cells, the plurality of storage cells being arranged in a plurality of rows and a plurality of columns; and
providing, from the input buffer to the CIM module, reshaped data configured for the CIM module.
18 . The method of claim 17 , wherein the input buffer includes a plurality of shift registers, wherein the data is bit-parallel data, wherein the input buffer configured to bit-wise transpose the data, wherein the receiving further includes:
loading the bit-parallel data in the plurality of shift registers; and wherein the providing the reshaped data further includes
providing to the CIM module, from a portion of the plurality of shift registers, a portion of the reshaped data such that the reshaped data is bit-serialized.
19 . The method of claim 17 , wherein a source of the data is clocked at a first frequency, wherein the CIM module is clocked at a second frequency, the input buffer is configured to convert the first frequency to the second frequency, the first frequency being a multiple of the second frequency.
20 . The method of claim 17 , wherein the input buffer includes at least one bank and wherein the providing further includes:
loading a portion of the data in each of the at least one bank to the CIM module in parallel.